Multiprotocol SerDes PMA

Overview

Key Features

• Supports over 30 protocols including CEI 6G & 11G SR, MR, LR, Ethernet 10GBASE-X/S/K/R, PCIe Gen1/2/3/4, V-by-One HS/US, CPRI, PON, OTN/OTU, 3GSDI, JESD204A/B/C, SATA1-3, XAUI, SGMII
• Programmable (De)Serialization width: 8, 10, 16, 20, 32, or 40 bit
• Tx ring PLL includes fractional multiplication, spread spectrum and Jitter Cleaner function for Sync-E and OTU
• Core-voltage line driver with programmable pre-and post-emphasis
• Out-of-band, electrical idle signaling capability for SAS, SATA, and PCIe
• Ultra-low-Latency optimized PMAs with in-PMA latency below 13UI (<1.3ns at 10.3Gbps): See this overview.
• Burst mode CDR with tCDR < 150UI
• Programmable CTLE and adaptive 5-Tap Decision Feedback Equalizer for poor channels
• Non-destructive eye monitor to measure eye opening at data slicer on chip

Benefits

• Excellent jitter performance with a ring PLL. In most cases we can use the on-die Xtal reference which saves an expensive clock chip. Our ring PLL IP can also be used to generate a PCIe2, PCIe3, PCIe4 or PCIe5 compliant reference clock for other PHYs. This eye diagram captured on the output of the PHY we developed for the PolarFire FPGA with a broad range of protocols validated shows the excellent signal integrity possible with our low power IP.
• Delivered including all supplies, ESD and RDL for your bump pitch ... simply drop into layout.
• Amongst the more than 25 different PMA IPs our customers have in production are several for JESD204A/B. This JESD204B 4-lane transmitter was developed to occupy one side of a 180nm wirebond packaged ADC. First silicon met the specification and runs up to 7.5Gbps/lane.
• A two-chip set receives three DVI signals and packages them to transmit over fiber, regenerating the same DVI stream at the far end
• Ring PLLs with wide continuous range and extremely low jitter using only an on-die Xtal reference enable PMAs with low power and low area
• Receiver jitter tolerance measured with TSMC 40 LP Multiprotocol PMA shows wide margin to protocols and fast tracking bandwidth.
• Easily meeting DisplayPort requirements.
• Excellent low jitter is stable over PVT using a ring PLL

Block Diagram

Applications

• Programmable devices needing to support over 30 different protocols
• AFE -- FPGA interfaces
• 10G-KR Ethernet
• SATA/SAS interfaces
• UHD-TV (4k TV) displays
• MFPs
• Scanners
• Semi-custom chip-chip interfaces
• Backplanes

Deliverables

• GDSII
• CDL Netlist (MG Calibre Compatible)
• Functional Verilog Model
• Liberty timing models (.lib)
• LEF
• Application Note with integration and production test guidelines
• Signal Integrity simulations using customer package models

Technical Specifications