Jitter Cleaner PLL Digital Loop Filter

Overview

The Silicon Creation "DPLL" is a digital loop filter/controller designed to be used in conjunction with Silicon Creations Fractional-N PLLs. The resulting dual-loop PLL can attenuate jitter in extremely noisy reference clocks (and "gapped clocks" such as in OTN SerDes repeater/switch systems) and multiply very low frequency clocks. The loop bandwidth of the combined PLL is determined by the digital loop filter and can be arbitrarily small while the quality of the output clock is determined by the connected Fractional-N PLL and its reference clock. The DPLL uses a modest number of gates and the resulting dual-loop PLL is fully integrated (no external components) with a total area little more than the embedded Fractional-N PLL.

Key Features

Automatically locks over an extremely wide input frequency range -- from <10Hz to maximum speed of standard cell gates available
Dual-loop PLL effective loop bandwidth can be arbitrarily small
Dual-loop PLL output frequency can be integer M/N multiples or sub-multiples of input frequency
Delivered as synthesizable RTL -- compatible with any process
Synthesizes to less than 20k gates (<0.02mm2 in 40n CMOS)
Frequency comparator for fast initial locking automatically switches to phase comparator for fine locking
State may be saved and pre-loaded for so output frequency is correct after power-down
Compatible with Silicon Creations LC-based and inverter ring based Fractional-N PLLs enabling output clocks with sub-ps Long Term Jitter
Dual-loop PLL system can use crystal reference or vitually any high-quality reference clock source
Self-timed -- uses feedback clock as system clock to achieve high time to digital phase comparison resolution

Benefits

Saves power and system cost:
Replaces expensive (>$10) external jitter cleaner PLL chips requiring off-chip differential buffers and receivers with silicon area costing just a few cents.
Reduces risk.

Block Diagram

Applications

Clock de-spreading for Video format converters.
Jitter cleaning for Synchronous Ethernet and Gapped Clock cleaning in OTU systems

Deliverables

Synthesizable RTL (Verilog)
Timing constraints
Documentation
Comprehensive support

Technical Specifications

Foundry, Node

Any

Maturity

Silicon Proven

Availability

Now

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