Serial ATA IP

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Compare 86 IP from 18 vendors (1 - 10)
  • Dual Serial ATA 1.5/3.0/6.0 Gbps Phy
    • Serial ATA fully compliant to Gen 1,Gen 2 and Gen3 SATA Phy Standards.
    • Transmit and receive data at 1.5Gbps, 3.0 Gbps and 6.0 Gbps.
    • High-speed differential reference clock
    • Low jitter clock synthesizers for clock distribution
  • Serial ATA I/II/III Host Controller IP Core Compliance Certified by UNH Labs
    • High Throughput
    • Low Latency
    • Connects to SAPIS compliant serial ATA Phy
    Block Diagram -- Serial ATA I/II/III Host Controller IP Core Compliance Certified by UNH Labs
  • Serial ATA Dual Host Controller
    • Physical Layer features
    • Link Layer features
    • Transport Layer features
  • Serial ATA I/II Device Controller IP Core
    • The Serial ATA Device Controller IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices.
    • The serial link employed is a high-speed differential layer that utilizes Gigabit technology and 8b/10b encoding.
    Block Diagram -- Serial ATA I/II Device Controller IP Core
  • Serial ATA (SATA) I/II PHY IP CORE
    • Supports 1.5 Gb/s (Gen 1) and 3.0 Gb/s (Gen 2) serial data rate
    • Compatible with Serial ATA II
    • Utilizes 10-bit or 20-bit parallel interface to transmit and receive Serial ATA data
    • Data and clock recovery from serial stream on the SATA bus
  • Dual Parallel to Serial ATA 1.5/3.0Gb/s PHY Core
    • Serial ATA fully compliant to Gen 1 and Gen 2 SATA PHY Standard.
    • Single and Dual data rate capable of transmit and receive at 1.5Gb/s and 3.0 Gb/s.
    • High-speed differential reference clock
    • Low jitter clock synthesizers for clock distribution
  • Serial ATA PHY
    • 1.5 / 3.0 Gbps
    • Complies with SATA 3.0 Specification
  • Serial ATA1.5/3.0 Gbps PHY IP Core
    • Includes support for the following processes: -TSMC 130nm LVOD -SMIC 130nm G
    • Compliant to the Serial ATA specification
    • Selectable 1.5 Gbps or 3.0 Gbps high-speed serial data communication
    • Supports hot swapping
  • Serial ATAIP- Host Controller
    • Compliant with the Serial ATA specification version 2.6
    • Supports 1.5 Gb/s (150 MB/s) or 3 Gb/s (300 MB/s) speeds
    • Supports Native Command Queuing (NCQ)
    • Support for Spread Spectrum Clocking (SSC)
  • SATA HOST CONTROLLER IIP
    • Supports SATA specs 2.5/2.6/3.0/3.1/3.2/3.3/3.4/3.5.
    • Fully synthesizable
    • Static synchronous design
    • Positive edge clocking and no internal tri-states
    Block Diagram -- SATA HOST CONTROLLER IIP
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Semiconductor IP