Serial ATA IP
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89
IP
from 17 vendors
(1
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10)
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Serial ATA Host Controller (1.5, 3.0, 6.0 Gb/s) 5th Generation
- High Performance
- AXI Interface
- Flexible
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Serial ATA Gen 3 Host Controller (1.5, 3.0, 6.0 Gb/s)
- High Throughput
- Low Latency
- Connects to SAPIS compliant serial ATA Phy
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Serial ATA Host Controller (1.5, 3.0, 6.0 Gb/s)
- High Throughput: 531 MBytes/sec Read, 505> MBytes/sec Write
- Low Latency: 66K IOPS Read, 67K IOPS Write (4k blocks)
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Serial ATA (SATA) I/II PHY IP CORE
- Supports 1.5 Gb/s (Gen 1) and 3.0 Gb/s (Gen 2) serial data rate
- Compatible with Serial ATA II
- Utilizes 10-bit or 20-bit parallel interface to transmit and receive Serial ATA data
- Data and clock recovery from serial stream on the SATA bus
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Serial ATA Bridge Controller (1.5, 3.0, 6.0 Gb/s)
- High Performance
- AXI Interface
- Flexible
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Serial ATA Host Controller (1.5, 3.0, 6.0 Gb/s) for Xilinx UltraScale
- High Throughput: 531 MBytes/sec Read, 505 MBytes/sec Write
- Low Latency: 66K IOPS Read, 67K IOPS Write (4k blocks)
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Serial ATA Dual Host Controller
- Physical Layer features
- Link Layer features
- Transport Layer features
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Dual Serial ATA 1.5/3.0/6.0 Gbps Phy
- Serial ATA fully compliant to Gen 1,Gen 2 and Gen3 SATA Phy Standards.
- Transmit and receive data at 1.5Gbps, 3.0 Gbps and 6.0 Gbps.
- High-speed differential reference clock
- Low jitter clock synthesizers for clock distribution
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Dual Parallel to Serial ATA 1.5/3.0Gb/s PHY Core
- Serial ATA fully compliant to Gen 1 and Gen 2 SATA PHY Standard.
- Single and Dual data rate capable of transmit and receive at 1.5Gb/s and 3.0 Gb/s.
- High-speed differential reference clock
- Low jitter clock synthesizers for clock distribution
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Serial ATA PHY
- 1.5 / 3.0 Gbps
- Complies with SATA 3.0 Specification