The Serial ATA Host Controller IP Core provides an interface to highspeed serial link replacements for the parallel ATA attachment of mass storage devices. The serial link employed is a highspeed differential layer that utilizes Gigabit technology and 8b/10b encoding.
This core is fully compliant to the Serial ATA 3.0 specification.
ARCHITECTURE
The Serial ATA Link and Transport Layer Core implements a serial ATA host interface which connects to a SATA PHY via a 10/20/40 bit interface and provides a Wishbone slave interface for register and DMA access.
It consists of the link layer module with 10/20/40 bit data paths to the physical layer and a transport layer module which connects to the system via a Wishbone slave interface.
SAPIS PHY INTERFACE
This interface connects to any SAPIS compliant serial ATA PHY. Power management and speed negotiation signals are included. The PHY interface is synchronous to the PHY clock domain, which may have a different clock frequency than the system clock domain. Synchronization is done by the Serial ATA Link and Transport Layer Core.
DMA HANDSHAKE
Simple handshake signals are provided to connect a DMA unit to the core module. The DMA requests will be asserted as soon as any transmit data is available or is needed in the core's data FIFO. The DMA unit will then access the data FIFO via the Wishbone slave interface. A system interrupt will inform host software on completion of a data transfer.
Automatic flow control mechanisms control data throttling to avoid underflow or overflow of the transmit data FIFO. The DMA unit (or host software) may work at any speed without the risk of data loss. Data FIFO thresholds can be adjusted to optimize the data flow control.
