SMS6000 is a fully integrated CMOS transceiver that handles the low level Serial ATA protocol and signaling. It contains all necessary Clock synthesis, Clock Recovery, Serializer, Deserializer, Comma detect for 8B/10B encoded data and Frame alignment functionalities. Digital controller interface is realized with a 10-bit parallel operation (Optional 20-bit Interface) that allows use of 150 MHz (300 MHz) reference Clock. The transceiver includes Signal Detect, COMRESET/COMINIT and COMWAKE Out-of-Band capability compliant with Serial ATA Specification requirements in addition to COMSAS Out-of-band Signal detection capability required by the Serial Attached SCSCI (SAS).
SMS6000 complies with the latest version of the SAPIS standard both as a PHY Core IP and for discrete Transceiver implementations.
SMS6000 implements the full requirements of Serial ATA 1.0a specification in terms of Power Management and Loopback functionality. Both Partial and Slumber power management modes are fully supported both in the digital portion and the AFE of the PHY for maximum power efficiency. Also all the Loopback functions such as Near-End Loopback and Far-End-Loopback are supported in addition to proprietary Loopback implementations for functional testing.
SMS6000 does not require any external Loop filter capacitor(s) for clock Synthesis PLL or Clock recovery circuitry making it immune to PCB related noise typically encountered, and provides a completely integrated solution.
