SMS6000 is a Serial ATA gen I and gen II compliant PHY IP which supports SAPIS and Serial Attached SCCI (SAS) specifications both at 1.5 Gbp/s and 3.0 Gbp/s.
Serial ATA (SATA) I/II PHY IP CORE
Overview
Key Features
- Supports 1.5 Gb/s (Gen 1) and 3.0 Gb/s (Gen 2) serial data rate
- Compatible with Serial ATA II
- Utilizes 10-bit or 20-bit parallel interface to transmit and receive Serial ATA data
- Data and clock recovery from serial stream on the SATA bus
- Optional 8b/10b encode/decode and error indication
- Near-End and Far-End Loop-back Support
- Embedded Bit Error Rate Testing Through PBRS generation and detection
- Supports HOST and DEVICE controller applications
- OOB Signal Detection for COMWAKE, COMRESET/COMINIT and COMSAS
- COMMA & Squelch Detect Support
- Power Management Support for Slumber and Partial PM Modes.
- Calibrated Internal RX, TX Termination Resistors
- Support for Serial Attached SCSI SAS Mode
- Compliant with SATA PHY Interface Specification (SAPIS)
- Full low cost, low power CMOS Implementation
Deliverables
- Bus Functional/Behavioral Model for the PHY.
- Hard Macro GDS.
- Netlist for LVS/DRC support.
- SOC Integration Plan.
- Test Plan.
Technical Specifications
TSMC
Pre-Silicon:
180nm
G
UMC
Pre-Silicon:
130nm
,
180nm
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