SATA Device IP Core (1.5, 3.0, 6.0 Gbps)

Overview

Key Features

• 10, 20 and 40 bit Phy interface
• Connects to SAPIS compliant serial ATA Phy
• Fully compliant to SATA Gen 1 (1.5 Gbps), Gen 2 (3.0 Gbps) and Gen 3 (6.0 Gbps)
• Wishbone slave interface for register access and FIFO/DMA data transfers
• Only very few FF's in the Phy clock domain, main part on the Wishbone clock
• 128 byte (32 double word) data FIFO (optional 256 byte)
• Parallel ATA legacy software compatibility
• Implements the Task File, the non-standard serial ATA status and control registers, specific device registers and native mode registers
• interrupt and DMA handshake (external DMA)
• 48-bit address feature set supported
• 8b/10b coding and decoding
• CONT and data scramblers to reduce EMI
• CRC generation and checking
• Auto inserted HOLD primitives
• Power management support (partial and slumber)
• Optional native mode programming model
• Many configuration options

Benefits

• Flexible
• Compact
• Cost-effective

Deliverables

• Verilog Source Code
• Test Bench
• Sample Synthesis scripts
• Documentation
• Reference Design

Technical Specifications