SRAM compiler IP
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482
IP
from 16 vendors
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10)
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Single Port SRAM Compiler GF22FDX Low Power
- Silicon proven Single Port SRAM compiler for GF22 FDX - Memory optimized for low power and supports body biasing.
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Single Port SRAM Compiler GlobalFoundries 55LPx Ultra-high density, low power, up to 320K bits
- Capacity to 320K bits
- Word width: 8 to 144 bits
- Address range: 32 to 8k
- Nominal voltage: 1.2V
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Single port SRAM Compiler - low power retention mode
- Uses low leakage devices and source biasing to minimize standby currents.
- Dedicated standy mode with built in source biasing for the memory array.
- Periphery and array supplies are isolated to allow power off of the perphery when in standy mode.
- .8V supply voltage
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Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k
- Reduce the die cost
- Unique architecture optimizing the periphery area for outstanding area gain
- Extend the battery life
- Leakage reduction thanks to careful design structures, optional retention mode and choice of SVT/HVT periphery
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Single Port SRAM compiler - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 640 kbits
- Source biasing implementation for low leakage
- 4 times less leakage compared to stand by mode
- 3 times less leakage compared to retention mode
- Designed with the latest uLL PRBC from TSMC and a mix of HVT and SVT MOS (dominated by SVT to reach high speed)
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Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 72 k
- Reduce the die cost
- Unique architecture optimizing the periphery area for outstanding area gain
- Extend the battery life
- Leakage reduction thanks to careful design structures, optional retention mode and choice of SVT/HVT periphery
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Single Port SRAM compiler - Memory optimized for ultra high density and low power - 3ML- compiler range up to 320 k
- Reach the highest density
- Thanks to smart periphery design
- using High density Pushed Rules Foundry bitcell
- use only 3 metal levels inside the memory
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Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k
- Migration of an existing architecture already available for other processes (90, 85, 55 nm)
- Smart periphery design to reach the highest density
- Memory designed with SVT MOS for periphery and SVT uHD PRBC from TSMC for memory core
- Ultra Low dynamic power
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Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 64 k
- Reduce the die cost
- Unique architecture optimizing the periphery area for outstanding area gain
- Extend the battery life
- Leakage reduction thanks to careful design structures, optional retention mode and choice of SVT/HVT periphery