IGMSHDY01A is a synchronous ULVT / LVT periphery high density single port SRAM compiler. It is developed with TSMC 5 nm 0.75 V/1.2 V CMOS LOGIC FinFET Compact Process. Different combinations of words, bits, and column-selected number (MUX) could be used to generate the most desirable configurations.
Given the desired size and timing constraints, the IGMSHDY01A compiler is capable of providing suitable synchronous SRAM instances models within minutes. It is capable of automatically generating the datasheets, Verilog behavioral simulation models, Place & Route (P & R) models, and test patterns for use in ASIC designs. The duty cycle length could be neglected as long as setup/hold time and minimum high/low pulse width requirements are satisfied. This allows a more flexible clock falling edge during each operation.
TSMC CLN5FF High Density Single Port SRAM Compiler
Overview
Key Features
- The High Density Single Port SRAM operates within voltage range from 0.675 V to 0.825 V and junction temperature range from -40 °C to 125 °C. The available supported macro size is configurable from 512 bits to 576K bits. The Compiler is divided into 1 groups according to their column selection numbers (Mux=8).
- ? Pins and metal layers
- – 1P3M (1X_h_1Xb_v): 3 metal layers used and top metal is MXb.
- – Power mesh supported with M3 pins
- ? Compilation options
- – MUX selection for the desired macro aspect ratio
- – Bit-write mask function (BWEB pin) that allows writing to designated bits in a word
- ? Power management
- – Sleep mode powers down most of the peripheral circuits for leakage reduction with data retention.
- – Deep sleep mode powers down most of the peripheral circuits for leakage reduction and retains memory array content with lower voltage.
- – Shutdown mode achieves highest leakage reduction without data retention.
- ? General features
- – High Current TSMC 6T 0.0257 um2 SRAM bit cell
- – Frequently used EDA model support
- – Column redundancy
- – Dual rail design to support Dynamic Voltage Frequency Scaling (DVFS) application
Technical Specifications
Foundry, Node
TSMC 5nm CLN5FF
Maturity
Avaiable on request
TSMC
Pre-Silicon:
5nm
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