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SDIO Host controller IP

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  • Block Diagram -- SD 4.1 SDIO 4.1 Host Controller IP
  • SD / SDIO / MMC Host Controller
    • Compliant with SD Host Controller Standard Specification Version 2.0
    • Compliant with SD Physical Layer Specification Version 2.0
    • Compliant with SDIO Specification 2.0
    • Compliant with eMMC Specification Version 4.41
    Block Diagram -- SD / SDIO / MMC Host Controller
  • SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller
    • Memory Card / Form Factors:
    • IP Details:
    Block Diagram -- SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller
  • SD 4.1 / SDIO 4.0 / eMMC 5.1 Host Controller
    • Fully compliant core with proven silicon
    • Premier direct support from Arasan IP core designers
    • Easy-to-use industry standard test environment
  • SD/eMMC Lite Host Controller IP
    • Compliant with the SD 6.0, SDIO 4.10 and eMMC 5.1 specifications and earlier versions
    • Supports advanced eMMC features including HS400 mode and built-in CQE with priority sensitive scheduling algorithm for high performance
    • Low power features with power gating and multi-power rails
    • Supports the host controller interface (HCI) specification for SD ensuring the usability of standard software drivers with support for SDMA, ADMA2 and ADMA3 modes
    Block Diagram -- SD/eMMC Lite Host Controller IP
  • SD/eMMC Host Controller IP
    • Compliant with the SD 6.0, SDIO 4.10 and eMMC 5.1 specifications and earlier versions
    • Supports advanced eMMC features including HS400 mode and built-in CQE with priority sensitive scheduling algorithm for high performance
    • Low power features with power gating and multi-power rails
    • Supports the host controller interface (HCI) specification for SD ensuring the usability of standard software drivers with support for SDMA, ADMA2 and ADMA3 modes
    Block Diagram -- SD/eMMC Host Controller IP
  • SD/eMMC Crypto Host Controller
    • Compliant with the SD 6.0, SDIO 4.10 and eMMC 5.1 specifications and earlier versions
    • Supports advanced eMMC features including HS400 mode and built-in CQE with priority sensitive scheduling algorithm for high performance
    • Low power features with power gating and multi-power rails
    • Supports the host controller interface (HCI) specification for SD ensuring the usability of standard software drivers with support for SDMA, ADMA2 and ADMA3 modes
    Block Diagram -- SD/eMMC Crypto Host Controller
  • SDIO Host IP
    • Compliant with SD Host Controller Specification version 6.0
    • Compliant with SDIO Physical Specification version 6.10
    • Compliant with Part E1 SDIO specification 4.10
    • Supports SDMA, ADMA2 and ADMA3 modes
  • Low-power SD/eMMC host controller IP provides advanced high-performance 32- and 64-bit AXI interface to the SoC
    • Compliant with SD HCI specification
    • CQE capable of reordering task execution based on priority
    • Data prefetching for back to back tasks—further improves random IOPS
    • Low-power features with power gating and multi-power rails
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