SDIO Host Controller IIP

Overview

The SDIO Host IIP core supports the SD Host Controller Specification version 4.0 and compatible with SDIO version 4.10 specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. SDIO HOST IIP is proven in FPGA environment. The host interface of the SDIO can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

SDIO Host Controller IIP is supported natively in Verilog and VHDL

Key Features

Compliant with SD Host Controller Specification version 4.0
Compliant with Part E1 SDIO specification 4.10
Supports SDMA, ADMA2 and ADMA3 modes
Supports 1-bit, 4-bit bus mode and SPI Bus mode
Supports all commands/response types
Supports SDR12, SDR25 ,DDR50, SDR 50 and SDR104 modes
Supports Single byte, Single block , Multi –block(finite and infinite) transfers
Supports read wait
Supports card detection
Fully synthesizable
Static synchronous design
Scan test ready
Simple interface allows easy connection to microprocessor/microcontroller devices
Optionally UHS - II support can be added

Benefits

Single site license option is provided to companies designing in a single site.
Multi sites license option is provided to companies designing in multiple sites.
Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Block Diagram

Deliverables

The SDIO HOST IP Controller is available in Source and netlist products.
The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
Easy to use Verilog Test Environment with Verilog Testcases
Lint, CDC, Synthesis, Simulation Scripts with waiver files
IP-XACT RDL generated address map
Firmware code and Linux driver package
Documentation contains User's Guide and Release notes.

Technical Specifications

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