IP Catalog > SDIO Host Controller

SDIO Host Controller IP

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Compare 30 IP from 10 vendors (1 - 10)
  • SDIO Host Controller IIP
    • Compliant with SD Host Controller Specification version 4.0
    • Compliant with Part E1 SDIO specification 4.10
    • Supports SDMA, ADMA2 and ADMA3 modes
    • Supports 1-bit, 4-bit bus mode and SPI Bus mode
    Block Diagram -- SDIO Host Controller IIP
  • SD / SDIO / MMC Host Controller
    • Compliant with SD Host Controller Standard Specification Version 2.0
    • Compliant with SD Physical Layer Specification Version 2.0
    • Compliant with SDIO Specification 2.0
    • Compliant with eMMC Specification Version 4.41
    Block Diagram -- SD / SDIO / MMC Host Controller
  • SD 4.1 / SDIO 4.1 / eMMC 4.51 Host Controller IP
    • The SD 4.1/SDIO 4.1 IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports three key memory card I/O technologies.
    • SD 4.1 Host Controller IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds.
    Block Diagram -- SD 4.1 / SDIO 4.1 / eMMC 4.51 Host Controller IP
  • SD 3.0 / SDIO 3.0 / eMMC 5.1 Host Controller IP
    • The SD 3.0 / eMMC 5.1 Host IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds.
    • The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead.
    Block Diagram -- SD 3.0 / SDIO 3.0 / eMMC 5.1 Host Controller IP
  • SD 3.0/SDIO 3.0/eMMC 4.51 Host Controller Software Stack
    • This is a production-ready software stack for Arasan’s SD 3.0/ SDIO 3.0/ eMMC 4.51 Host Controller IP that is used to connect to SD, SDIO, or eMMC devices.
    • The SD 3.0/eMMC 4.51 stack can also be used for validating a device during its development and integration life cycles thereby helping designers to reduce the time to market for their product.
    Block Diagram -- SD 3.0/SDIO 3.0/eMMC 4.51 Host Controller Software Stack
  • SD Card Host Controller IP
    • The SD Card Host IP f is a highly integrated host controller IP solution that supports three key memory card I/O technologies:
    • The SD Card Host IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds.
    Block Diagram -- SD Card Host Controller IP
  • eMMC Host Controller IP
    • The eMMC Host controller IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds.
    • The eMMC 4.51 Host IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead.
    Block Diagram -- eMMC Host Controller IP
  • SD 4.1 Host Controller Software Stack
    • This is a production-ready stack for Arasan’s eMMC Host Controller IP that is used to connect to SD, SDIO, or eMMC devices.
    • The SD4/SDIO4/eMMC 4.5.1 Stack can also be used for validating a device during its development and integration life cycles thereby helping designers to reduce the time to market for their product.
    Block Diagram -- SD 4.1 Host Controller Software Stack
  • SD 4.1 eMMC 5.1 Dual Host Controller IP
    • The SD 4.1/SDIO 4.0/eMMC 5.0 Host IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports three key memory card I/O technologies:
    • The SD 4.1 / eMMC 5.1 Host IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds. The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead. In addition, a host can utilize this IP to boot directly from an attached eMMC memory, thereby simplifying system initialization during power up. The host interface is based on a standard 32-bit AHB bus which is used to transfer data and configure the SD 4.1 / eMMC5.1 Host IP.
    • eMMC 5.1 is backward compatible to the previous versions.
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    Block Diagram -- SD 4.1 eMMC 5.1 Dual Host Controller IP
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