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SD 5.1 eMMC 5.1 IP

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Compare 34 IP from 5 vendors (1 - 10)
  • SD 5.1 / eMMC 5.1 Host Controller IP
    • SD IP Features :
    • Support SD system specification version 5.1
    • Support Application Performance Class 1.
    • Backward compatible to SD2.0 host
    Block Diagram -- SD 5.1 / eMMC 5.1 Host Controller IP
  • SD 4.1 / SDIO 4.0 / eMMC 5.1 Host Controller
    • Fully compliant core with proven silicon
    • Premier direct support from Arasan IP core designers
    • Easy-to-use industry standard test environment
  • eMMC 5.1 Host Controller
    • Compliant with eMMC Specification Version 5.0
    • Supports one of the following System/Host Interfaces: AHB, AXI or OCP
    Block Diagram -- eMMC 5.1 Host Controller
  • IO 3.3V eMMC in GF (22nm)
    • Completely hardened PHY solution along with programmable delay chains & I/Os
    • Fully selectable output impedance
    • Compliant with eMMC 5.1 (JESD84-B51A) and SDIO 3.0 JEDEC Standard
    • Automotive G1/G2 supported, ASIL-B certified
  • High-Density eMRAM Compiler TSMC 22ULL
    • eMRAM compiler enabling low-power designs requiring high memory capacity
  • Low-power SD/eMMC host controller IP provides advanced high-performance 32- and 64-bit AXI interface to the SoC
    • Compliant with SD HCI specification
    • CQE capable of reordering task execution based on priority
    • Data prefetching for back to back tasks—further improves random IOPS
    • Low-power features with power gating and multi-power rails
  • TSMC N3P 1.8V IO Platform supporting cells
    • Compliant with eMMC 5.1 HS400, SD 6.0 SDR104, DDR50, JESD8-7a (1.2V/1.8V) and JESD8c.01 (3.3V)
    • Fully integrated hard macro with high speed IOs and DLL/delay lines
    • Fine resolution DLL/delay lines for HS400 strobe and HS200/SDR104 auto-tuning
    • Easy to integrate with the highly optimized Synopsys SD/eMMC Host Controller IP, providing a complete low risk solution
    Block Diagram -- TSMC N3P 1.8V IO Platform supporting cells
  • TSMC N3P SD/eMMC PHY North/South Poly Orientation
    • Compliant with eMMC 5.1 HS400, SD 6.0 SDR104, DDR50, JESD8-7a (1.2V/1.8V) and JESD8c.01 (3.3V)
    • Fully integrated hard macro with high speed IOs and DLL/delay lines
    • Fine resolution DLL/delay lines for HS400 strobe and HS200/SDR104 auto-tuning
    • Easy to integrate with the highly optimized Synopsys SD/eMMC Host Controller IP, providing a complete low risk solution
    Block Diagram -- TSMC N3P SD/eMMC PHY North/South Poly Orientation
  • SD/eMMC - TSMC 7FF, North/South Poly Orientation
    • Compliant with eMMC 5.1 HS400, SD 6.0 SDR104, DDR50, JESD8-7a (1.2V/1.8V) and JESD8c.01 (3.3V)
    • Fully integrated hard macro with high speed IOs and DLL/delay lines
    • Fine resolution DLL/delay lines for HS400 strobe and HS200/SDR104 auto-tuning
    • Easy to integrate with the highly optimized Synopsys SD/eMMC Host Controller IP, providing a complete low risk solution
    Block Diagram -- SD/eMMC - TSMC 7FF, North/South Poly Orientation
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