SD 5.1 eMMC 5.1 IP
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34
IP
from 5 vendors
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10)
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SD 4.1 eMMC 5.1 Dual Host Controller IP
- The SD 4.1/SDIO 4.0/eMMC 5.0 Host IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports three key memory card I/O technologies:
- The SD 4.1 / eMMC 5.1 Host IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds. The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead. In addition, a host can utilize this IP to boot directly from an attached eMMC memory, thereby simplifying system initialization during power up. The host interface is based on a standard 32-bit AHB bus which is used to transfer data and configure the SD 4.1 / eMMC5.1 Host IP.
- eMMC 5.1 is backward compatible to the previous versions.
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SD 3.0 / SDIO 3.0 / eMMC 5.1 Host Controller IP
- The SD 3.0 / eMMC 5.1 Host IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds.
- The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead.
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SD 5.1 / eMMC 5.1 Host Controller IP
- SD IP Features :
- Support SD system specification version 5.1
- Support Application Performance Class 1.
- Backward compatible to SD2.0 host
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IO 3.3V eMMC in GF (22nm)
- Completely hardened PHY solution along with programmable delay chains & I/Os
- Fully selectable output impedance
- Compliant with eMMC 5.1 (JESD84-B51A) and SDIO 3.0 JEDEC Standard
- Automotive G1/G2 supported, ASIL-B certified
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SD 3.0 I/O Pad Set
- TSMC 16nm
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High-Density eMRAM Compiler TSMC 22ULL
- eMRAM compiler enabling low-power designs requiring high memory capacity
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Low-power SD/eMMC host controller IP provides advanced high-performance 32- and 64-bit AXI interface to the SoC
- Compliant with SD HCI specification
- CQE capable of reordering task execution based on priority
- Data prefetching for back to back tasks—further improves random IOPS
- Low-power features with power gating and multi-power rails
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TSMC N3P 1.8V IO Platform supporting cells
- Compliant with eMMC 5.1 HS400, SD 6.0 SDR104, DDR50, JESD8-7a (1.2V/1.8V) and JESD8c.01 (3.3V)
- Fully integrated hard macro with high speed IOs and DLL/delay lines
- Fine resolution DLL/delay lines for HS400 strobe and HS200/SDR104 auto-tuning
- Easy to integrate with the highly optimized Synopsys SD/eMMC Host Controller IP, providing a complete low risk solution
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TSMC N3P SD/eMMC PHY North/South Poly Orientation
- Compliant with eMMC 5.1 HS400, SD 6.0 SDR104, DDR50, JESD8-7a (1.2V/1.8V) and JESD8c.01 (3.3V)
- Fully integrated hard macro with high speed IOs and DLL/delay lines
- Fine resolution DLL/delay lines for HS400 strobe and HS200/SDR104 auto-tuning
- Easy to integrate with the highly optimized Synopsys SD/eMMC Host Controller IP, providing a complete low risk solution
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SD/eMMC - TSMC 7FF, North/South Poly Orientation
- Compliant with eMMC 5.1 HS400, SD 6.0 SDR104, DDR50, JESD8-7a (1.2V/1.8V) and JESD8c.01 (3.3V)
- Fully integrated hard macro with high speed IOs and DLL/delay lines
- Fine resolution DLL/delay lines for HS400 strobe and HS200/SDR104 auto-tuning
- Easy to integrate with the highly optimized Synopsys SD/eMMC Host Controller IP, providing a complete low risk solution
