Radiation-hardened I/O IP

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Compare 9 IP from 3 vendors (1 - 9)
  • Full Radiation-Hardened ESD Library in GF 12nm LP/LP+
    • Full ESD Library for Powers and I/O
    • I/O Protection 
    • Full Library is Latch-up proven to 200mA at -40C to 125C 
    • Radiation Hardened 64 MeV proton test and >1.3E+09 flux
  • 1.8V and 3.3V Radiation-Hardened GPIO with Optimized LDO in GF 12nm
    • A radiation-hardened GlobalFoundries 12nm LP/LP+ Flip-Chip IO library with both 1.8V and 3.3V GPIO, fail-safe GPI, analog cell, and associated ESD. Also features an LDO optimized for use with 3.3V GPIO.
    • This radiation-hardened, by design, library features both a 1.8 and 3.3V GPIO with multiple drive strengths of 2mA, 4mA, 8mA, and 16mA, along with a full-speed output enable function.
    Block Diagram -- 1.8V and 3.3V Radiation-Hardened GPIO with Optimized LDO in GF 12nm
  • Wirebond I/O Library in TSMC 130nm
    • A radiation-hardened TSMC 130nm Wirebond I/O Library with 3.3V GPIO, 3.3V LVDS TX & RX, 3.3V I2C ODIO, 3.3V Analog cell, OTP cell, and associated ESD.
    • Key attributes of this silicon-proven, radiation hardened I/O library include an extended operational temperature range (-50C to 200C), a sleep retention mode, and a built in power regulation PMOS device for core VDD.
    Block Diagram -- Wirebond I/O Library in TSMC 130nm
  • Radiation-Hardened eFPGA
    • Radiation-Hardened by Design (RHBD): Built to operate in space and defense applications, ensuring reliability under extreme conditions.
    • Customizable eFPGA IP: Tailored to specific mission requirements with adaptability to various process nodes and foundries.
    • High Reliability: Designed to withstand Total Ionizing Dose (TID) and Single Event Effects (SEE).
  • GF12 - 0.8V SLVS Rad-Hard Transceiver in GF 12nm
    • This SLVS I/O Library delivers a robust, high-performance solution for high-speed differential signaling in GlobalFoundries 12nm process technology.
    • Designed for optimal signal integrity, this 0.8V SLVS transceiver features fast rise and fall times, low propagation delay, and built-in pre-emphasis to enhance signal quality over longer traces.
    • With support for data rates up to 3Gbps, it enables reliable, low-power communication while maintaining excellent noise immunity.
    Block Diagram -- GF12 - 0.8V SLVS Rad-Hard Transceiver in GF 12nm
  • GF12 - 0.8V LVDS Rad-Hard Transceiver in GF 12nm
    • The 2.5Gbps LVDS transceiver in GlobalFoundries LP/LP+ is designed for high-speed, low-power data transmission in radiation-intensive environments.
    • Engineered with a Rad-Hard by Design approach, the Rad-Hard cells have been proton tested to 64 MeV with a flux exceeding 1.3E+09, and is latch-up proven to 200mA across -40C to 125C, ensuring robust immunity against TID, SEE, and SEL effects.
    Block Diagram -- GF12 - 0.8V LVDS Rad-Hard Transceiver in GF 12nm
  • ARINC 429 Transmitter DO-254 IP Core
    • The ARINC 429 Tx IP Core implements a transmitter as specified in the ARINC Specification 429 Part 1-17.
    • The ARINC 429 Rx Core has been developed to DAL A according to the DO-254 / ED-80 and is accompanied by a Certification Kit.
    Block Diagram -- ARINC 429 Transmitter DO-254 IP Core
  • ARINC 429 Receiver DO-254 IP Core
    • Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
    • Fully compliant to Bosch’s CAN Specification 2.0 (Sep 1991)
    • Time Triggered Communication (TTC) support according to ISO 11898-1 (2003-12-01)
    • Tested as specified in the ISO 16845 (2004-03-15)
    Block Diagram -- ARINC 429 Receiver DO-254 IP Core
  • 10/100/1000 Ethernet MAC DO-254 IP Core
    • The 10/100/1000 Ethernet MAC Controller DO-254 IP Core implements the Media Access Control as specified in the IEEE 802.3-2008 specification.
    • The Ethernet MAC Controller has been developed to DAL A according to the DO-254 / ED-80 and is accompanied by a Certification Kit
    Block Diagram -- 10/100/1000 Ethernet MAC DO-254 IP Core
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