PCI Express PHY IP
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PCI Express 4.0 PHY
- Compiles with PCIe 4.0, 3.1, 2.1, 1.1 and PIPE 4.4.1 specifications
- Supports all power-saving modes (P0, P0s, P1, P2) as defined in PIPE 4.4.1 specifications
- Supports L1 PM/CPM substates with CLKREQ#
- Supports the separate REFCLK Independent SSC (SRIS) architecture
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PCI Express Gen 4 PHY
- Support 16GT 8GT 5GT 2.5GT data rate
- Compliant with PCI Express 4.0, 3.1, 2.1, 1.1 and PIPE 4.2 standards
- x1, x2, x4, x8, x16 lane configuration with bifurcation
- Multi-tap adaptive programmable continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE)
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PCI Express PHY
- Quad PCIe 16/8/5/2.5 Gbps per lane
- Tight control over termination resistor (~50 Ohm) with on chip calibration
- Tight skew control of 1UI between lanes of the PMA
- 3-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
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PCI Express PIPE PHY Transceiver
- Supports 2.5Gb/s serial data rate
- Utilizes 8-bit or 16-bit parallel interface to transmit and receive PCI Express data
- Full Support for Auxiliary Power (Vaux) for Energy aware systems like Multi-Port Host Controllers
- Data and clock recovery from serial stream on the PCI Express bus
