PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.18um G2 process
Overview
PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY, UMC 0.18um GII Logic (RVT) process.
Technical Specifications
Foundry, Node
UMC 180nm G2
UMC
Pre-Silicon:
180nm