Pci expess phy IP

Compare 445 IP from 24 vendors (1 - 10)

PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
- Supports 2.5Gb/s serial data rate
- Utilizes 8-bit or 16-bit parallel interface to transmit and receive PCI Express data
- Full Support for Auxiliary Power (Vaux) for Energy aware systems like Multi-Port Host Controllers
- Data and clock recovery from serial stream on the PCI Express bus
PCI Express 4.0 PHY
- Compiles with PCIe 4.0, 3.1, 2.1, 1.1 and PIPE 4.4.1 Specifications
- Supports all power saving modes (P0, P0s, P1, P2) as defined in PIPE 4.4.1 spec.
PCI Express Gen 4 PHY
- Support 16GT 8GT 5GT 2.5GT data rate
- Compliant with PCI Express 4.0, 3.1, 2.1, 1.1 and PIPE 4.2 standards
- x1, x2, x4, x8, x16 lane configuration with bifurcation
- Multi-tap adaptive programmable continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE)
PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.13um HS/FSG process
PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.18um G2 process
PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.18um G2 process
PCI Express Gen2 PHY IP, PCIe Gen-2, 4 Lanes, UMC 90nm SP process
PCI Express Gen2 PHY IP, PCIe Gen-2, 1 Lanes, UMC 90nm SP process
PCI Express Gen2 PHY IP, PCIe Gen-2, 1 Lanes, UMC 55nm SP process
Samsung 28nm FDSOI USB3.0 and PCIE2 combo PHY
- USB3.0 Super-Speed: Universal Serial Bus 3.0 Specification, Revision 1.0
- PCI Express: PCI Express Base Specification, Revision 2.0

PCI Expess PHY IP