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Noc Interconnect IP

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Compare 13 IP from 7 vendors (1 - 10)
  • Network-on-Chip (NoC) Interconnect IP
    • AMBA AXI / APB / AHB protocol compliant
    • Configurable number of masters and slaves
  • High speed NoC (Network On-Chip) Interconnect IP
    • The ORBIT On-Chip Interconnect (OIC) delivers exceptional performance, and SoC design flexibility based on automated end-to-end interconnect generation flow.
    • It enables high-speed routing with pre-calculated routing path details and supports higher speed, low latency, and floorplan flexibility.
    Block Diagram -- High speed NoC (Network On-Chip) Interconnect IP
  • NoC System IP
    • Packetization allows a reduction of the wire count
    • Significant reduction of the complexity of large crossbars by partitioning them into smaller ones
    • Introduction of pipelining to links with heavy loads, allowing the NoC to operate faster
    Block Diagram -- NoC System IP
  • Tessent NoC Monitor
    • Full transaction and trace-level visibility of traffic
    • Wide range of measurements, analytics statistics: transactions, bus cycles, latency, duration, beats, concurrency
    Block Diagram -- Tessent NoC Monitor
  • Coherent Network-on-Chip (NOC)
    • Node Protocols: ACE4, ACE5 and CHI
    • Architected to significantly reduce routing congestion for many-core systems
    • Integrated with SkyeChip’s Home Agent and swappable with any other proprietary coherency handlers
    • Supports operating frequencies up to 2GHz with assists in high frequency timing closures
  • Non-Coherent Network-on-Chip (NOC)
    • Node Protocols: AXI4, AXI5, AXI-Stream, APB and proprietary protocols
    • Architected to reduce routing congestion and to ease high frequency timing closure
    • Supports operating frequencies up to 2GHz
    • Supports source synchronous and synchronous clocking topologies
  • Ncore 3 Coherent Network-on-Chip (NoC)
    • Supports multiple coherent agents, including Armv9 and RISC-V CPU clusters
    • AMBA CHI-E, CHI-B and ACE interoperability, as well as ACE-Lite and AXI
    • Low-latency proxy caches for efficient and quick integration of hardware accelerators into the coherent domain
    • Configurable last-level caches
    Block Diagram -- Ncore 3 Coherent Network-on-Chip (NoC)
  • FlexNoC 5 Interconnect IP
    • Physical Awareness for faster timing closure
    • Higher margins
    • Fewer wires
    Block Diagram -- FlexNoC 5 Interconnect IP
  • NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
    • Easy to integrate the NoC Silicon IP using interface
    • N master and M slave ports based on customer requirement
    • Supports wide range of memory map.
    Block Diagram -- NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
  • LPDDR5X/5/4X/4 combo PHY at 12nm
    • Compliant with JEDEC JESD209-5C for LPDDR5x/5/4x/4 with PHY standards
    • Delivering up to 8533Mbps
    • DFI 5.1 specification PHY Interface Compliant
    • Support up to 4 ranks
    • Multiple frequency states
    Block Diagram -- LPDDR5X/5/4X/4 combo PHY at 12nm
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