For scalable and area-efficient heterogeneous cache coherent systems.
The Arteris Ncore Cache Coherent Interconnect IP offers unparalleled scalability, configurability, and, with the Ncore Safety Option, data protection and hardware duplication capabilities to help meet up to ISO 26262 ASIL B and D requirements against random hardware faults.
Version 3.6 of the Ncore Cache Coherent Interconnect IP adds support for the AMBA CHI-E protocol as well as interoperability of CHI-B and ACE, and ACE-Lite protocols in the same coherent system. AXI is also supported and Ncore will enable it to access CPU caches in an IO coherent way.
Ncore is scalable, supporting up to 16 coherent CPU clusters or other coherent agents.
It incorporates multiple configurable snoop filters, multiple configurable proxy caches, and multiple clock domains, using a modular, distributed architecture to provide system architects the most advanced technology and more degrees of freedom to innovate.
Ncore 3 Coherent Network-on-Chip (NoC)
Overview
Key Features
- Supports multiple coherent agents, including Armv9 and RISC-V CPU clusters
- AMBA CHI-E, CHI-B and ACE interoperability, as well as ACE-Lite and AXI
- Low-latency proxy caches for efficient and quick integration of hardware accelerators into the coherent domain
- Configurable last-level caches
- The Functional Safety (FuSa) Option helps meet up to ISO 26262 ASIL B and D requirements against random hardware faults
- Ncore is ISO 26262 certified
Benefits
- Accelerate Machine Learning And Neural Network Soc Designs:AMBA CHI-E and ACE interoperability allow more flexible integration of new and legacy processing elements, leveraging investments in existing ACE IP. Ncore’s proxy caches allow more efficient use of die area than the dedicated SRAMs or scratchpad memories used in traditional pipelined neural network design, while also offering the means to simplify software.
- Develop Iso 26262-Compliant Complex Socs:Achieving the desired ISO 26262 ASIL for a complex system is extremely difficult and often results in additional software burdens. Using the optional Ncore Safety Option: Integrates hardware functional safety mechanisms in the interconnect, trapping errors and faults at the lowest possible level, and simplifying software and the FMEDA process.
- Scalability & Flexibility: Ncore Cache Coherent Interconnect IP supports multiple coherent agents, allowing for the design of highly flexible SoC platforms that can be tailored to meet changing product requirements.
Block Diagram
Applications
- Automotive, Mobility, Wireless, Consumer Electronics, IoT, Server, Networking, and Industrial SoCs that require low-latency and high bandwidth Cache Coherency.