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Multiport Memory Controller IP

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Compare 33 IP from 15 vendors (1 - 10)
  • Universal Multiport Memory Controller - LPDDR 3/2 Controller
    • Compliant with AXI V4.0 specification
    • Compliant with DFI 3.1 specification
    • Compliant with JEDEC LPDDR2 and LPDDR3 standards
    • Support for 8, 16, 32 SDRAM bus width, for a total memory data path width up to 64 bits
    Block Diagram -- Universal Multiport Memory Controller - LPDDR 3/2 Controller
  • Multi-Port Memory Controller (DDR/DDR2/SDRAM)
    • Soft Direct Memory Access (SDMA) support
    • Double Data Rate (DDR/DDR2) and Single Data
    • Rate (SDR) SDRAM memory support
    • DIMM support (registered and unbuffered)
  • DO-254 DDR Memory Controller 1.00a
    • DDR, DDR2, DDR3, and LPDDR (Mobile DDR) memory standards support
    • Up to 800 Mb/s (400 MHz double data rate) performance
    • Up to four MCB cores in a single Spartan-6 device
    • Configurable dedicated multi-port user interface to FPGA logic
  • Avalon Multi-port DDR2 Memory Controller
    • 200 / 333 MHz (400/666 Mbps) Cyclone/Stratix DDR2 memory performance
    • DDR2 Memory Devices
    • From 1 to 16 Avalon-MM local bus port interfaces
    • Memory bandwidth utilization in excess of 95%
    Block Diagram -- Avalon Multi-port DDR2 Memory Controller
  • Streaming Multi-port SDRAM Memory Controller
    • 200/333 MHz (400/666 Mbps) Cyclone / Stratix memory performance
    • SDR, DDR, DDR2, and Mobile DDR SDRAM memory devices
    • Up to 10 native RD or WR ports
    • Memory data width: 8/16/32/64-bit
    Block Diagram -- Streaming Multi-port SDRAM Memory Controller
  • Avalon Multi-port SDRAM Memory Controller IP Core
    • 200 / 333 MHz (400/666 Mbps) Cyclone / Stratix DDR2 memory performance
    • SDR, DDR, DDR2 and Mobile DDR SDRAM Memory Devices
    • From 1 to 16 Avalon-MM local bus port interfaces
    • Memory bandwidth utilization in excess of 95%
    Block Diagram -- Avalon Multi-port SDRAM Memory Controller IP Core
  • Multi-Port Front-End
    • Provides a multi-port interface to Rambus’s Memory Controller Cores
    • Performs command reordering to maximize memory throughput and prioritize high priority requests
    • User configurable number ports
    • Request priority set on a per request basis
  • Video DMA Core
    • Simplifies interface and control of VFBC and streaming video interfaces to provide customers with an easy integration of DMA functionality for video systems.
  • AXI Interface Core
    • Provides high performance interface to AXI
    • Handles conversion of bus width/ speed to memory width/speed
    • Can be used in single port or multi port configurations
    • Provided with a Bus Functional Model (testbench)
  • Display Controller - LCD / OLED Panels (AHB-Lite Bus)
    • Wide range of programmable LCD Panel resolutions:
    • Support for 1 Port TFT LCD Panel interfaces:
    • Programmable frame buffer bits-per-pixel (bpp) color depths:
    • Programmable Output format support:
    Block Diagram -- Display Controller - LCD / OLED Panels (AHB-Lite Bus)
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