MPMC is a fully parameterizable memory controller that supports SDRAM/DDR/DDR2 memory. MPMC provides access to memory for one to eight ports, where each port can be chosen from a set of Personality Interface Modules (PIMs) that permit connectivity into PowerPC® 405 processor and MicroBlaze™ processors using CoreConnect® PLBv4.6 and the MPMC Native Port Interface (NPI) structures, and well as a a Memory Interface Block (MIB) PIM (PPC440MC) for the PowerPC 440 Processor.
Multi-Port Memory Controller (DDR/DDR2/SDRAM)
Overview
Key Features
- Soft Direct Memory Access (SDMA) support
- Double Data Rate (DDR/DDR2) and Single Data
- Rate (SDR) SDRAM memory support
- DIMM support (registered and unbuffered)
- Error Correcting Code (ECC) support
- Parameterizable number of ports (1 to 8)
Technical Specifications
Related IPs
- I2C Controller IP – Slave, Parameterized FIFO, Hs-Mode (3.4 Mbps) AXI/AHB/APB/Avalon Buses or direct to/from Registers or Memory
- SPI XIP Flash Memory Controller IP – Programmable IO & Execute-In-Place (XIP) via second AMBA Interface
- Intel 8259A Functional Equivalent Programmable Interrupt Controller
- Intel 8259A Functional Equivalent Programmable Interrupt Controller
- Avalon Multi-port SDRAM Memory Controller IP Core
- Multi-Port Front-End