Avalon Multi-port DDR2 Memory Controller

Overview

The Avalon Multi-port DDR2 Memory Controller IP Core is designed for maximizing the performance of an Altera Nios II processor in Avalon® multi-master streaming data systems. Advanced design features enable maximum system clock rates using low speed FPGA's and standard memory devices, lowering your production cost, and saving you money.

The Avalon-MM slave ports can be independently clocked allowing the system to be partitioned and optimized to achieve maximum performance. Supporting post memory read and write cycles, the data FIFO's effectively double memory bandwidth on sequential address or FIFO cache hits. FIFO depth can be tailored for either streaming or random access.

The core is optimized for Altera® Cyclone, Arria and Stratix device families of field programmable logic devices. The Avalon Slave ports are configured with Qsys GUI which greatly simplifies the design of Avalon-MM based SOC systems.

The DDR2 Memory Controller handles all memory tasks, including initialization and refresh cycles. It is designed to operate asynchronous to the local port clocks enabling the memory to be clocked at its peaked rated frequency maximizing system performance.

Key Features

200 / 333 MHz (400/666 Mbps) Cyclone/Stratix DDR2 memory performance
DDR2 Memory Devices
From 1 to 16 Avalon-MM local bus port interfaces
Memory bandwidth utilization in excess of 95%
Avalon Pipelined and Burst transfers
Avalon local bus width from 8 to 128-bits
Memory data width: 8/16/32/64-bit
Configurable FIFO depth: 16 to 2048 bytes
Intelligent SDRAM burst caching controller minimizes wait-states
PCB layout independent DDR2 Round-Trip capture scheme
Requires only single PLL with 2 clock outputs
Independent system/memory time domain clocking
Supports: Cyclone II, III, IV-E, IV-GX, V, Stratix II, II-GX, III, IV/IV-GX and Arria GX/II-GX

Benefits

MegaWizzard GUI for ease of configuration
Requires only single PLL with 2 clock outputs
DQS data capture clocking simplifies DDR2 PCB constraints and eliminates dedicated data capture PLL
Configurable FIFO maximizes performance of streaming data applications
Configurable memory and local bus data width optimizes cost
Independent time domain clocking optimizes memory bandwidth
Round-robin (dafault) and user configurable bus arbitration schemes
Synopsis TimeQuest support ensures timing closure

Block Diagram

Deliverables

Altera SOPC Builder Ready & Qsys Configuration GUI
Supports Synopsys TimeQuest timing analyzer
VHDL IP functional simulations models
On Die Termination (ODT) improves signal integrity
IP Core license includes 1 year of maintenance updates
Altera OpenCore Plus evaluation

Technical Specifications

Availability

Available for immediate sale

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