Mobiveil IP

The AXI MATRIX-IP component is a multi-layer interconnect implementation of the AXI protocol, which is designed for high-performance, high-frequency system designs.
AXI MATRIX-IP is highly configurable with the capacity to handle up to 16 Masters and Slaves. IP can be configured to support AXI3, AXI4-Lite or AXI4

The UMMC Controller is a highly flexible and configurable design. It is targeted for high bandwidth access and low power consumption such as next generation mobile, DDR/LPDDR networking and consumer applications.
The controller architecture is carefully tailored to achieve reliable high-frequency operation with dynamic power management and rapid system debug capabilities.

The Universal NVM Express Controller (UNEX) is highly flexible and configurable design targeted for both Enterprise and client class solutions that unlock the current and future potential of PCIe-based SSDs.
The UNEX controller core efficiently supports multi-core architectures ensuring thread(s) may run on each core with their own queue and interrupt without any locks required.
It provides support for end-to-end data protection, security and encryption as well as robust error reporting and management capabilities.

This controller supports AP Memory’s UHS series of high speed PSRAM devices which can clock frequencies of upto 1066 MHz.
This controller enables smooth integration of APMemory’s UHS OPI PSRAM memory device chips into various new-gen devices made with mobile and wearable low power SoCs’.
This memory controller implementation is designed to give the user full flexibility for driving the memory control signals and timing adjustment for data sampling.

The HyperRAM controller supports Winbond’s HyperBus based HyperRAM devices
This controller enables smooth integration of Winbond’s HyperBus HyperRAM memory chips into various new-gen SoCs’.

The RapidIO Verification IP (VIP) provides highly capable compliance verification solution for the RapidIO protocol.
The RapidIO VIP is system Verilog (SV) based and supports standard Universal Verification Methodology (UVM).
It can be easily combined with any other UVM compliant verification components to extend a broader verification environment.

The 5G NR LDPC Decoder IP Core offers a robust solution for LDPC decoding, featuring a dedicated LDPC decoder block for optimal performance.
It employs the Min-Sum LDPC decoding algorithm to ensure efficient decoding.
The core allows for programmable internal bit widths at compile time, though the default values are usually sufficient.

This controller supports AP Memory’s Xccela open standard Bus for digital interconnect and data communications, suitable for non-volatile and volatile memories such as PSRAM.
This controller enables smooth integration AP memory’s of Xccela PSRAM memory chips into various new-gen devices made with mobile and wearable low power SoCs’.
This memory controller implementation is designed to give the user full flexibility for driving the memory control signals and timing adjustment for data sampling.