Mobiveil's Universal NVM Express Controller (UNEX) is highly flexible and configurable design targeted for both Enterprise and client class solutions that unlock the current and future potential of PCIe-based SSDs. The UNEX controller core efficiently supports multi-core architectures ensuring thread(s) may run on each core with their own queue and interrupt without any locks required. It provides support for end-to-end data protection as well as robust error reporting and management capabilities. The controller architecture is carefully tailored to optimize link and throughput utilization, latency, reliability, power consumption, and silicon footprint.
Mobiveil’s UNEX controller can be used along with Mobiveil LDPC Encoder/Decoder, DDR5/4/3 (UMMC) and Enterprise Flash controller (EFC) IPs for a complete NVMe/SSD implementation.
The UNEX controller comes with three flavors:
• Native UNEX Controller with proprietary Control and Data path interfaces
• UNEX Controller with AXI Control and Data path interfaces for easy adoption in an SoC implementation
• UNEX Controller with Streaming Control and Data path interface (AXI4 ST) for easy adoption in an SoC implementation with PCIe HIP or any third-party PCIe Controllers
UNEX Controller design is independent of implementation tools and target technology. Mobiveil solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally.
Universal NVM Express Controller (UNEX)
Overview
Key Features
- Compliant to NVM Express 2.0 specification
- Compliant with AXI4-ST/AXI Interface towards PCIe Interface
- Compliant with AXI4 Interface towards memory subsystem interface
- Support for configurable number of IO Queues
- Support for configurable Queue depth
- Support for Round Robin or Weighted Round Robin with Urgent Priority arbitration mechanism
- Host memory page size support of 128MB
- Efficient and streamlined command handling
- Supports Fused Operations
- Supports All Optional Admin Commands
- Supports All Optional NVM Commands
- Supports Multi-Path IO and Namespace Sharing capabilities
- Supports End-to-End Data Protection
- Supports for configurable number of DMA Engines
- Supports Reservations
- Supports for Zoned namespace command set and Key Value command set
- Supports Copy command and Lock command
- Optional AXI interfaces for NVMe implementation in SoC
- Well defined Command Interface for local CPU to perform subsystem initialization and to handle all non-hardware accelerated commands
Benefits
- Superior architecture-optimized for high performance, low latency, low power and low gate count
- Feature rich, highly flexible, scalable, configurable and timing friendly design
- Ease of integration
- Verified with leading VIP
Block Diagram
Deliverables
- Verilog RTL
- HVL based test bench and behavioral models
- Test cases
- Protocol checkers, bus watchers and performance monitors
- Configurable synthesis shell
- NVM Device FW Stack
- Documentation
Technical Specifications
Maturity
Platinum (In volume Production)
Availability
NOW