The RapidIO Verification IP (VIP) provides highly capable compliance verification solution for the RapidIO protocol. The RapidIO VIP is system Verilog (SV) based and supports standard Universal Verification Methodology (UVM). It can be easily combined with any other UVM compliant verification components to extend a broader verification environment. The RapidIO VIP uses a layered architecture which is divided in to a Logical, Transport and Physical layers. RapidIO monitors handle protocol checking and fully comply with RapidIO specification. It provides hooks for implementing functional coverage, scoreboard and end to end checker. RapidIO VIP provides extensive compliance test suite which verifies all possible protocol scenarios. It simplifies the verification flow and reduces the verification effort. It can be used to verify designs at IP, SoC or system level setup. Stimulus generation is fully automated and gives large flexibility for user to generate directed and random test scenarios. User can constrain the randomization at different levels and functional coverage helps gauging the effectiveness of the randomization.
Configurable Options
- RapidlO Specification Version
- Baud rate selection
- Lane configuration
- Addressing mode
- Device ID mode
- Idle configuration
VIP Atributes
- Layered architecture
- PE and PL model selection
- Call backs
- Error injection and detection
- Transactions and symbols monitor log
- Multiple levels of verbosity for debugging
- Register Model
