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MIPI DCS IP

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Compare 25 IP from 8 vendors (1 - 10)
  • TFT/LCD/MIPI Display Controller and Composition Engine
    • Programmable display resolutions up to 32Kx32K
    • Compressed framebuffer support
    • Variable Frame-Rate support
    Block Diagram -- TFT/LCD/MIPI Display Controller and Composition Engine
  • MIPI DSI-2 Receiver Controller v2.0
    • DSI-2 Controllers Support
    • • MIPI specification of Display Serial Interface (DSI) v2
    • • MIPI specification of D-PHY
    • • MIPI specification of C-PHY
    Block Diagram -- MIPI DSI-2 Receiver Controller v2.0
  • MIPI DSI-2 Transmit Controller v2.0
    • Fully compliant to MIPI standard
    • Small footprint
    • Code validated with Spyglass
    Block Diagram -- MIPI DSI-2 Transmit Controller v2.0
  • MIPI DSI Transmit Controller v1.3
    • Compliant with the following MIPI specifications
    • DSI Host-side (display module) interface supports
    • Application Processor Connectivity and video/command processing
    • AHB Interface for register configuration and monitoring using programmed IO
    Block Diagram -- MIPI DSI Transmit Controller v1.3
  • MIPI DSI Receiver Controller v1.3
    • Compliant with the following MIPI specifications
    • DSI Host-side interface supports
    • Display Panel Connectivity and video/command processing
    Block Diagram -- MIPI DSI Receiver Controller v1.3
  • MIPI DSI-2 Transmit Controller v1.0
    • Fully compliant to MIPI standard
    • Small footprint
    • Code validated with Spyglass
    Block Diagram -- MIPI DSI-2 Transmit Controller v1.0
  • MIPI DSI-2 RX Controller
    • Compliant with the following specifications:  MIPI DSI-2 Specification v1.1;  MIPI D-PHY Specification v2.0, 4 D-PHY data lanes; Display Command Set (DCS) Specification v1.3 and  APB Specification v3.0
    •  Supports ULPS/LPDT/BTA mode
    Block Diagram -- MIPI DSI-2 RX Controller
  • MIPI DSI-2 TX Controller
    • Compliant with the following specifications:  MIPI DSI-2 Specification v1.1, MIPI D-PHY Specification v2.0, 4 D-PHY data lanes, Display Command Set (DCS) Specification v1.3 and APB Specification v3.0
    •  Supports ULPS/LPDT/BTA mode
    Block Diagram -- MIPI DSI-2 TX Controller
  • RGB to MIPI DSI Display Interface Bridge
    • Supports MIPI DSI and MIPI CSI-2 outputs up to 6 Gbp: 1, 2 or 4 data lanes
    • Supports parallel MIPI DPI, CMOS, RAW and RGB interfaces at up to 300 MHz
    • Supports CSI-2 compatible video formats (RAW, RGB, and YUV):
    • Supports DSI compatible video formats (RGB):
    Block Diagram -- RGB to MIPI DSI Display Interface Bridge
  • One Input to Two Output MIPI DSI Display Splitter Bridge
    • Supports MIPI DSI up to 6 Gbps per MIPI D-PHY
    • Provides one or two MIPI DSI outputs
    • Supports all MIPI DSI data types
    • Provides a DCS (Display Command Set) controller to program the display, ROM data used only for DSI in HS or LPDT mode – ROM is programmable by user
    Block Diagram -- One Input to Two Output MIPI DSI Display Splitter Bridge
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