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MIPI DSI-2 Verification IP

Overview

MIPI DSI-2 Verification IP provides an smart way to verify the MIPI DSI-2 bi-directional two-wire/three-wire bus. The SmartDV's MIPI DSI-2 Verification IP is fully compliant with version 2.0 MIPI Alliance specification for serial Interface and provides the following features.

MIPI DSI-2 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

MIPI DSI-2 Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Full MIPI DSI-2 Tx and Rx functionality.
  • Supports 2.0 MIPI DSI-2 Specification.
  • Support both DPHY and CPHY
  • Supports MIPI DBI specification
  • Supports MIPI DCS specification
  • Supports all types of D-PHY short packets
  • Supports all types of D-PHY long packets
  • Supports all types of C-PHY short packets
  • Supports all types of C-PHY long packets
  • Supports all lane configuration
  • Supports 8 lane configuration of DPHY layer
  • Supports 4 lane configuration of CPHY layer
  • Supports multiple packets per transmission
  • Supports differential and single ended mode of operation
  • Supports PPI interface
  • Supports all BTA commands
  • Supports Link Distribution Function
  • Supports skew calibration
  • Supports data scrambling
  • Supports below data rates in DPHY layer
    • 80 to 1500 Mbps per lane without deskew calibration
    • Upto 2500Mbps per lane with deskew calibration
    • Upto 12000Mbps per lane with equalization
  • Supports below data rates in CPHY layer
    • 17.1 Gbps for 3 lanes
    • 5.7 Gbps for 1 lane
  • Supports Display Stream Compression (DSC)
  • Various kind of Tx and Rx errors generation and detection
    • SoT error
    • Sync error
    • Word count error
    • Sync length error
    • Checksum error
    • ECC error
  • Supports detection of all timeouts and injection of various timeout errors
  • Supports both high speed and low power packet transmission and reception
  • Supports fine grain control of timing parameters
  • Status counters for various events in bus.
  • Operates as a Tx,Rx, or both.
  • Monitor,Detects and notifies the testbench of all protocol and timing errors.
  • Callbacks in node transmitter, receiver and monitor for user processing of data.
  • MIPI DSI-2 Verification IP comes with complete test suite to test every feature of MIPI DSI-2 specification.
  • Functional coverage for complete MIPI DSI-2 features

Benefits

  • Faster testbench development and more complete verification of MIPI DSI-2 designs.
  • Easy to use command interface simplifies testbench control and configuration of Tx,Rx and monitor
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

MIPI DSI-2 Verification IP Block Diagram

Deliverables

  • Complete regression suite containing all the MIPI DSI-2 testcases.
  • Examples showing how to connect various components, and usage of Tx,Rx and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

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