MIPI DSI-2 Transmitter Controller IP Core

Overview

Key Features

Compliant with the following MIPI specifications

• Display Serial Interface (DSI-2) version 1.0
• Display Pixel Interface (DPI-2) version 2.00
• Display Bus Interface (DBI) version 2.00
• Display Command Set (DCS) version 1.3
• D-PHY version 1.2
• CPHY 1.1 and D-PHY version 2.0 (Combo PHY)

DSI TX (Processor Host) interface supports

• Connectivity to D-PHY through PPI Interface
• 1 to 4 data lane support
• Hi-Speed (HS) transmit from 80 Mbps to 2.5Gbps per lane
• Low Power (LP) receive/transmit from/to device at 10 Mbps
• Continuous and stoppable clocks on clock lane
• Bus turnaround with contention and fault recovery
• Switching to and from Low Power (LP) and Ultra-low Power (ULPS) modes
• EOT enable/disable mechanisms
• Multiple packets per transmission with interleaved data stream
• Programmable error injection in Verification IP and error detection in design IP
• Supports flexibility in setting polarity for DPI Interface signals

Application Processor Connectivity and video/command processing

• DPI or DBI, depending on panel or display unit architecture
• Generic command support
  • Generic parallel interface for sending and receiving vendor-specific information to and from the display driver logic in the display module
  • Support for all generic read/writes over DBI/Generic interface
• Video mode support
  • Supports wide range of display resolution and pixel formats
  • Supported display resolutions: QQVGA, QCIF, QVGA, CIF,VGA,WVGA, XGA, 1080p, QXGA, QSXGA
  • Burst mode and non-burst transfers over DPI interface
• DBI support
  • Supports 8/9/16-bit data transfer in DBI Type B interface
  • Supports all DCS commands

AHB Interface for register configuration and monitoring using programmed IO

Benefits

• Fully compliant to MIPI standard
• Small footprint
• Code validated with Spyglass
• Functionality ensured with comprehensive verification
• Product quality proven with silicon
• Premier direct support from Arasan IP core designers

Block Diagram

Deliverables

• Verilog HDL of the IP Core
• Synthesis scripts
• Verification environment
• User guides for design and verification

Technical Specifications