MIPI DSI Synthesizable Transactor

Overview

Key Features

• Full MIPI DSI Transmitter and Receiver functionality.
• Supports MIPI DSI v1.3 and MIPI DSI-2 v1.1 Specifications.
• Supports PPI interface.
• Operates as a Transmitter, Receiver, or both.
• Supports all types of DPHY short packets
• Supports all types of DPHY long packets
• Supports all types of CPHY short packets
• Supports all types of CPHY long packets
• Supports all lane configuration
• Supports multiple packets per transmission
• Supports differential and single ended mode of operation
• Supports sync event payloads
• Supports Display Stream Compression (DSC)
• Supports MIPI DSI-2 Specification
• Support both DPHY and CPHY
• Full MIPI DSI-2 Tx and Rx functionality
• Supports MIPI DBI specification
• Supports MIPI DCS specification
• Supports all BTA commands
• Supports skew calibration
• Supports data scrambling
• Supports detection of all timeouts and injection of various timeout errors
• Supports both high speed and low power packet transmission and reception
• Supports fine grain control of timing parameters
• Various kind of Transmitter and Receiver errors generation and detection
• SoT error
• Sync error
• Word count error
• Sync length error
• Checksum error
• ECC error
• Status counters for various events in bus.

Benefits

• Compatible with testbench writing using SmartDV's VIP
• All UVM sequences/testcases written with VIP can be reused
• Runs in every major emulators environment
• Runs in custom FPGA platforms

Block Diagram

Deliverables

• Synthesizable transactors
• Complete regression suite containing all the MIPI DSI testcases
• Examples showing how to connect various components,and usage of Synthesizable Transactor
• Detailed documentation of all DPI,class,task and functions used in verification env
• Documentation contains User's Guide and Release notes

Technical Specifications