HiSPi IP
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IP
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3
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Camera Combo Receiver - 5.0Gbps 8-Lane - TSMC 12FFC, 7FF
- The CL12842M8RM3AM5AIP5000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processor) and DSP.
- The CL12842M8RM3AM5AIP5000 is designed to support data rate in excess of maximum 5Gbps utilizing SLVS-EC ver.2.0 / MIPI D-PHY ver.1.2 / HiSPi / sub-LVDS / CMOS 1.8V interface specification.
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SMIC 55nm sub-LVDS Receiver
- Supports Aptina HiSPi, Panasonic LVDS, or Sony LVDS parallel input signal
- 10 data channels / 2 clock channel integrated
- Maximum serial data rate per channel: 1Gbps
- Supports up to 20-bit CMOS parallel input (DVP input mode)
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SMIC 55nm sub-LVDS Receiver
- Supports Aptina HiSPi, Panasonic LVDS, or Sony LVDS parallel input signal
- 8 data channels / 2 clock channel integrated
- Maximum serial data rate per channel: 1Gbps
- Supports up to 16-bit CMOS parallel input (DVP input mode)
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GLOBALFOUNDRIES 28nm SLP sub-LVDS Receiver
- Supports Aptina HiSPi, Panasonic LVDS, or Sony LVDS parallel input signal
- 4 data channels / 1 clock channel integrated
- Maximum serial data rate per channel: 1Gbps
- Supports up to 8-bit CMOS parallel input (DVP input mode)
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Camera 6/7-mode Combo Receiver - 1G/1.5Gbps
- The CL12684KM4-8-12-16R3AM6-7ZIP is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to Host System.
- The CL12684KM4-8-12-16R3AM6-7ZIP is designed to support data rate in excess of maximum 1Gbps utilizing sub-LVDS / mini-LVDS / LVDS / HiSPi(SLVS-400, HiVCM) / MIPI-DPHY / CMOS-1.8V / CMOS-3.3V interface specification.
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MIPI DPHY-TX - GlobalFoundries 22FDX process
- Data rate per lane: High-Speed mode 80M~2.5G bps, Low-Power mode 10Mbps
- Silicon proven in GlobalFoundries 22FDX process
- Compliant to the MIPI D-PHY spec v1.2
- Support HiSPi-SLVS TX compatible mode