SMIC 55nm sub-LVDS Receiver

Overview

Key Features

• Supports Aptina HiSPi, Panasonic LVDS, or Sony LVDS parallel input signal
• 8 data channels / 2 clock channel integrated
• Maximum serial data rate per channel: 1Gbps
• Supports up to 16-bit CMOS parallel input (DVP input mode)
• Each channel configurable independently
• Controllable 100? on-chip termination resistor
• De-serializes the serial inputs with a configurable ratio (8 / 10 / 12 / 14 / 16)

Technical Specifications