SMIC 55nm sub-LVDS Receiver

Overview

The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors. The receiver consists of PHY only.

Key Features

  • Supports Aptina HiSPi, Panasonic LVDS, or Sony LVDS parallel input signal
  • 8 data channels / 2 clock channel integrated
  • Maximum serial data rate per channel: 1Gbps
  • Supports up to 16-bit CMOS parallel input (DVP input mode)
  • Each channel configurable independently
  • Controllable 100? on-chip termination resistor
  • De-serializes the serial inputs with a configurable ratio (8 / 10 / 12 / 14 / 16)

Technical Specifications

Foundry, Node
SMIC 55nm
Maturity
Pre-Silicon
SMIC
Pre-Silicon: 55nm G , 55nm LL
×
Semiconductor IP