Forward Error Correction IP

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Silicon IP (144)
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Compare 167 IP from 38 vendors (1 - 10)

VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
- VESA DisplayPort 1.4 compliant
- Reed-Solomon RS (254,250) FEC, 10-bit symbols
- Two-way interleaving for 1-, 2- and 4-lane modes (4-lane mode requires 2 FEC IP core instances)
- DisplayPort main 8b/10b encoder included (Tx only)
- Status and control can be done with signals or optionally via an integrated APB register module (Rx)
25G IEEE 802.3by Reed-Solomon Forward Error Correction
- Run-time switchable between IEEE802.3by and 25G Ethernet Consortium Schedule 3 specification mode
- Low latency
- Accessible as integrated feature in the 25G Ethernet Subsystem
- Configuration and status bus
50G IEEE 802.3 Reed-Solomon Forward Error Correction
- Low latency
- Accessible as an integrated feature in the 50G Ethernet Subsystem
- Configuration and status bus
- Selectable AXI4-Lite interface for status output
32G Fibre Channel (32GFC) Reed-Solomon Forward Error Correction
- Low latency design
- Configuration and status bus
- Example reference design demonstrating of RS-FEC and GT Wizard cores
- ECC RAM option
IEEE 802.3bj Reed-Solomon Forward Error Correction
- Low latency
- Supports 100 Gigabits
- Configuration and status bus
- Selectable AXI4-Lite interface for status output
Error Correction IP
PCIe Gen 6 controller IP
- Designed to the latest PCI Express 6.0 (64 GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1/3.0 (8 GT/s), and PIPE 6.x (8, 16, 32, 64 and 128-bit) specifications
- Supports SerDes Architecture PIPE 10b/20b/40b/80b width
- Supports original PIPE 8b/16b/32b/64b/128b width
JESD204 Verification IP
- This JESD204 Verification IP provides an advanced and efficient solution for verifying and debugging these standards in a UVM simulation environment.
- The verification IP helps reduce time to test, accelerate verification process and ensures a high quality for the end-product.
Simulation VIP for PCIe
- Device Type
- Root Complex, End Point, Legacy End Point, Switch, PHY DUT, Bridge
- Interface
- Serial, Parallel (8-bit, 10-bit, 128-bit, and 130-bit), PIE8, PIPE 3.0, PIPE 4.0, PIPE 4.3, PIPE 4.4.x, PIPE 5.x, PIPE 6.0
SLVS-EC Verification IP
- Full SLVS-EC transmitter device and receiver device functionality.
- SLVS-EC supports version 2.0 specification.
- Supports the following system topologies between CIS and DSP
- Basic Topology