IP Catalog > Forward Error Correction

Forward Error Correction IP

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Compare 170 IP from 37 vendors (1 - 10)
  • VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
    • VESA DisplayPort 1.4 compliant
    • Reed-Solomon RS (254,250) FEC, 10-bit symbols
    • Two-way interleaving for 1-, 2- and 4-lane modes (4-lane mode requires 2 FEC IP core instances)
    • DisplayPort main 8b/10b encoder included (Tx only)
    • Status and control can be done with signals or optionally via an integrated APB register module (Rx)
    Block Diagram -- VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
  • 25G IEEE 802.3by Reed-Solomon Forward Error Correction
    • Run-time switchable between IEEE802.3by and 25G Ethernet Consortium Schedule 3 specification mode
    • Low latency
    • Accessible as integrated feature in the 25G Ethernet Subsystem
    • Configuration and status bus
  • 50G IEEE 802.3 Reed-Solomon Forward Error Correction
    • Low latency
    • Accessible as an integrated feature in the 50G Ethernet Subsystem
    • Configuration and status bus
    • Selectable AXI4-Lite interface for status output
  • 32G Fibre Channel (32GFC) Reed-Solomon Forward Error Correction
    • Low latency design
    • Configuration and status bus
    • Example reference design demonstrating of RS-FEC and GT Wizard cores
    • ECC RAM option
  • IEEE 802.3bj Reed-Solomon Forward Error Correction
    • Low latency
    • Supports 100 Gigabits
    • Configuration and status bus
    • Selectable AXI4-Lite interface for status output
  • Block Diagram -- Error Correction IP
  • DVB-S2-LDPC-BCH
    • Irregular parity check matrix
    • Layered decoding
    • Minimum sum algorithm
    • Soft decision decoding
    • BCH decoder works on GF (2m) where m=16 or 14 and corrects up to t errors, where t = 8, 10 or 12
    Block Diagram -- DVB-S2-LDPC-BCH
  • oFEC Encoder and Decoder
    • OpenROADM oFEC (Open Forward Error Correction) is a core element of the OpenROADM initiative, providing a standardized, open-source FEC solution for high-speed coherent optical networks.
    • The oFEC IP cores deliver high coding gain through a fully parallel, pipelined decoder architecture with 3 soft-decision (SD) and 2 hard-decision (HD) decoding steps. It supports data rates from 200G to 800G, including Probabilistic Constellation Shaping (PCS) modes to enhance spectral efficiency, noise tolerance, and transmission reach.
    Block Diagram -- oFEC Encoder and Decoder
  • Multi-channel DVB-C / J83 FEC encoder
    • The CMS0044 J.83abc/DVB-C Cable FEC Encoder combines all of the channel coding and Forward Error Correction functions specified by DVB-C and by J83 Annexes A B and C.
    • It is designed to interface to external modulators or advanced upconverting DACs such as the Analog Devices AD9789.
    Block Diagram -- Multi-channel DVB-C / J83 FEC encoder
  • Low Latency Ethernet 100G MAC and PHY Intel® FPGA IP Core
    • Intel® offers ultimate flexibility, scalability, and configurability with the Low Latency 100G Ethernet Intel® FPGA IP core targeted to network infrastructure and data centers.
    • The Low Latency 100G Ethernet Intel® FPGA IP core is compliant with the IEEE 802.3ba-2010 standard, it includes a media access control (MAC), PHY, physical coding sublayer (PCS), physical medium attachment (PMA), and an optional forward error correction (FEC) block.
    • It also includes IEEE 1588v2 timestamping support and the capability to drive backplanes on supported Intel® Stratix® and Intel® Arria® FPGAs. This IP can be used for chip-to-chip interfaces using copper interconnect or optical transceiver modules

     

    Block Diagram -- Low Latency Ethernet 100G MAC and PHY Intel® FPGA IP Core
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