25G IEEE 802.3by Reed-Solomon Forward Error Correction
Overview
Xilinx® offers the 25 Gigabit IEEE 802.3by Reed-Solomon Forward Error Correction (RS-FEC) IP core for data center and enterprise applications. This core is designed to the IEEE 802.3by and 25G Ethernet Consortium Schedule 3 specification and connects seamlessly to the Xilinx soft 25G Ethernet Subsystem IP on Virtex® UltraScale™, Virtex UltraScale+™, Kintex® UltraScale+, and Zynq® UltraScale+ devices.
Key Features
- Run-time switchable between IEEE802.3by and 25G Ethernet Consortium Schedule 3 specification mode
- Low latency
- Accessible as integrated feature in the 25G Ethernet Subsystem
- Configuration and status bus
- Selectable AXI4-Lite interface for status Output
- Transcode Bypass mode for direct access to RS encoder/decoder
- Example reference design demonstrating 25G Ethernet IP with RS-FEC
- ECC RAM option
Technical Specifications
Related IPs
- IEEE 802.3bj Reed-Solomon Forward Error Correction
- 50G IEEE 802.3 Reed-Solomon Forward Error Correction
- 32G Fibre Channel (32GFC) Reed-Solomon Forward Error Correction
- VESA DisplayPort 1.4 Forward Error Correction (FEC) Receiver
- VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
- HDMI 2.1 Forward Error Correction (FEC) Receiver