32G Fibre Channel (32GFC) Reed-Solomon Forward Error Correction
Overview
The Xilinx® LogiCORE™ 32G Fibre Channel (32GFC) RS-FEC IP core implements the Reed-Solomon Forward Error Correction (RS-FEC) sublayer as described in the INCITS Fibre Channel Framing and Signaling T11/15-253v2 specification.
Key Features
- Low latency design
- Configuration and status bus
- Example reference design demonstrating of RS-FEC and GT Wizard cores
- ECC RAM option
- Supports all features required for CPRI v7.0 operation
Technical Specifications
Related IPs
- IEEE 802.3bj Reed-Solomon Forward Error Correction
- 50G IEEE 802.3 Reed-Solomon Forward Error Correction
- 25G IEEE 802.3by Reed-Solomon Forward Error Correction
- VESA DisplayPort 1.4 Forward Error Correction (FEC) Receiver
- VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
- HDMI 2.1 Forward Error Correction (FEC) Receiver