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Die-to-Die PHY IP

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Search (63)
Compare 63 IP from 10 vendors (1 - 10)
  • TSMC CLN3FFE GLink 2.3LL Die-to-Die PHY
    • 56 full-duplex lanes per slice
    • 6-Slice/2-Slice PMA included in the analog hard macro
    • Lane repair
  • Die-to-Die PHY
    • The NuLink technology delivers low-power and high-performance D2D IP core products, which support multiple industry standards and are available on both standard and advanced packaging.
    Block Diagram -- Die-to-Die PHY
  • UCIe Die-to-Die PHY
    • High Bandwidth Density and Data Rates
    • Package Configurability
    • Energy Efficiency
    • Fully Integrated Solution
    Block Diagram -- UCIe Die-to-Die PHY
  • TSMC CLN5FF GLink 2.0 Die-to-Die PHY
    • 32 full-duplex lanes per slice
    • 8 slices are included in the analog hard macro
    • 1:8 mode with 256-bit data width or 1:16 mode with 512-bit data width for user interface
    • VALID and READY handshake mechanism
  • TSMC CLN5FF GLink 2.3LL Die-to-Die PHY
    • 56 full-duplex lanes per slice
    • 8 slices are included in the analog hard macro
    • 1:8 mode with 448-bit data width or 1:16 mode with 963-bit data width for user interface
    • VALID and READY handshake mechanism
  • TSMC CLN7FF GLink-3D Die-to-Die Slave PHY
    • Supports SoIC (3DFabric) CoW and WoW assembly
    • Supports face to face and face to back with the same GDSII
  • TSMC CLN5FF GLink-3D Die-to-Die Master PHY
    • Supports SoIC (3DFabric) CoW and WoW assembly
    • Supports face to face and face to back with the same GDSII
    • Supports point to multi-point (multi-Slave) communication
    • Up to 5 Gbps/bond (2.5 GHz DDR) data rate
  • TSMC CLN6FF/7FF Die-to-Die Interface PHY
    • 32 full-duplex lanes per slice
    • 8 slices are included in analog hard macro
    • Lane repair
  • Die-to-Die, AIB 2.0 PHY Ported to Intel 16, North/South (vertical) poly orientation
    • Delivers up to 4Gbps per pin with up to bidirectional 2 Tbps/mm of die edge
    • High-bandwidth, low-power, low-latency multi-channel PHY in applications requiring connections between dies within a package
    • Compliant with Intel Advanced Interface Bus (AIB) v1.1 standard
    • Compliant with IEEE 1149.1 (JTAG), 1149.6 (AC JTAG) for easy integration with SoC testability framework
    Block Diagram -- Die-to-Die, AIB 2.0 PHY Ported to Intel 16, North/South (vertical) poly orientation
  • Die-to-Die, High Bandwidth Interconnect PHY Ported to TSMC N7 X24
    • Delivers up to 4Gbps per pin with up to bidirectional 2 Tbps/mm of die edge
    • High-bandwidth, low-power, low-latency multi-channel PHY in applications requiring connections between dies within a package
    • Compliant with Intel Advanced Interface Bus (AIB) v1.1 standard
    • Compliant with IEEE 1149.1 (JTAG), 1149.6 (AC JTAG) for easy integration with SoC testability framework
    Block Diagram -- Die-to-Die, High Bandwidth Interconnect PHY Ported to TSMC N7 X24
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Semiconductor IP