Eliyan uses its NuLink technology to develop die-to-die PHY IP products to support multiple standards (including UCIe and BoW) and multiple packaging types (including advanced packaging and standard packaging).
For Standard Packaging, Eliyan has a family of high-bandwidth interface IP cores that are designed to be integrated into ASIC designs to connect two dies (chiplets) on the same standard organic/laminate package substrate. Eliyan’s PHY technologies with patented implementation techniques enable the same levels of performance and power as those provided by advanced packaging options, while providing benefits to system design, cost, thermal, test, yield, and production cycle-time by utilizing industry standard packaging. In many applications this eliminates the need for advanced packaging technologies such as silicon interposers or silicon bridges.
Die-to-Die PHY
Overview
Key Features
- The NuLink PHY IP cores for standard packaging are designed for standard organic/laminate packages with bump pitches from 100um to 130um.
- Eliyan has NuLink PHY IP products for industry standards (including UCIe and BoW) as well as unique value-added products including UMI™ and SBD.
- The NuLink PHY IP cores typically have 64 data lanes with configuration and bump map layout dependent on the PHY type (UCIe, BoW, UMI, SBD).
Block Diagram
Applications
- Chiplets connected on standard organic packages without large silicon interposers or silicon bridges but with interposer-like bandwidth/power/latency.
- SiP applications that benefit from up to at least four times the substrate area compared to the largest silicon interposer and thus a far higher number of chiplets in the package, resulting in major performance and power advantages.
- ASIC designs where a Network on Chip is split across two or more chiplets.
- Applications that benefit from placement flexibility to mix and match chiplets of different dimensions.
- Chiplet applications–such as HBM—where there must be physical separation between a hot ASIC and heat-sensitive dies.