IP Catalog > Interface IP > Die to Die IP > Other > TSMC CLN5FF GLink 2.3LL Die-to-Die PHY

TSMC CLN5FF GLink 2.3LL Die-to-Die PHY

Overview

IGAD2DY04A is a high-speed die-to-die interface PHY which transmits data through TSMC advanced packaging solutions: Integrated Fan-Out (InFO) with RDL interconnect and Chip-on-Wafer-on-Substrate (CoWoS®) with silicon interposer. IGAD2DY04A contains 56 TX lanes and 56 RX lanes per slice and supports 8 slices in one PHY. Each TX/RX lane can support up to 17.2 Gbps data rate. In summary, IGAD2DY04A offers a full-duplex data transmission with extremely low power and up to 963.2 Gbps data rate per slice in both directions.
Each TX/RX slice contains PMA and PCS modules. PMA supports serialization, de-serialization, data transmission, eye training, and lane repair functions. PCS provides data bus inversion (DBI), CRC check, and FIFO functions. One PLL is also included in IGAD2DY04A to generate an 8.5 GHz high-speed clock for data transmission.
IGAD2DY04A is designed and fabricated in TSMC 5 nm FF CMOS process with 1.2 V analog supply voltage for PLL/PMA and 0.75 V analog/digital supply voltages. Independent low power mode for PLL and slices is available.

Key Features

  • 56 full-duplex lanes per slice
  • 8 slices are included in the analog hard macro
  • 1:8 mode with 448-bit data width or 1:16 mode with 963-bit data width for user interface
  • VALID and READY handshake mechanism
  • Flow control between TX and RX
  • Data bus inversion
  • CRC check
  • Data replay to ensure no error found in RX
  • Programmable data scrambling for smoothing current consumption profile
  • Built-in test pattern and checker
  • Lane repair
  • EHOST: APB, I2C, and JTAG register interface
  • Built-in PLL
  • ~0.3 (TBD) pJ/bit power consumption
  • 1.2 V analog supply voltage for PLL/PMA and 0.75 V analog/digital supply voltage
  • Independent low power mode for analog blocks
  • Operating junction temperature: -40 °C ~ 125 °C
  • Process: TSMC 5 nm 0.75 V/1.2 V CMOS LOGIC FinFET Process
  • Metal Scheme: 1P17M (1X_h_1Xb_v_1Xe_h_1Ya_v_1Yb_h_5Y_vhvhv_2Yy2Yx2R)
  • Analog hard macro size: 3050 um x 1076 um (3.281 mm2) for North-South direction macro and
  • 1113 um x 3050 um (3.39 mm2) for East-West direction macro
  • Logic gate count: 4.2 M
  • Supports both horizontal and vertical GDS orientation
  • Special Layer & Device: High R Resistance, ULVT

Technical Specifications

Foundry, Node
TSMC 5nm CLN5FF
Maturity
Avaiable on request
TSMC
Pre-Silicon: 5nm
Request Info

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