IP Catalog > Die-to-Die (D2D) PHY

Die-to-Die (D2D) PHY IP

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Search (8)
Compare 8 IP from 6 vendors (1 - 8)
  • 40G UltraLink D2D PHY
    • Innovative mixed-signal architecture to achieve high bandwidth, ultra low latency and low power 
    • Flexible data rate from 20Gbps to 40Gbps 
    • Built-in self-test features to ensure “known good die” 
    • Interoperable between different technology nodes and foundries 
    • Easy routing and straightforward integration 
    • Achieves better than 10-15 bit error rate (BER) without requiring forward error correction (FEC) 
    • Integrated scrambling and lane de-skew functionality 
    • Supports -40ºC to 125ºC industrial temperature range 
    Block Diagram -- 40G UltraLink D2D PHY
  • 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
    • High Bandwidth Density and Data Rates
    • Package Configurability
    • Energy Efficiency
    • Fully Integrated Solution
    Block Diagram -- 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
  • Chiplet Interconnect - Die-to-die interconnect IP solutions for advanced and standard packaging applications
    • High data rate of 2–24 Gb/s
    • Very low power of < 0.375 pJ/bit @ 2–16 Gb/s 0.5-V VDDQ
    • Very low latency of < 2 ns PHY-to-PHY
    • Support for 2:1, 4:1, 8:1, 12:1 and 16:1 serialization and deserialization ratios
  • D2D Controller addon for D2D SR112G PHY with CXS interface
    • Low Latency controller for die-to-die connectivity
    • Supports PAM-4 and NRZ PHY signaling mode in all data rates
    • Reduces BER with optional FEC configurations
    • Supports Arm® AMBA® CXS interface
    Block Diagram -- D2D Controller addon for D2D SR112G PHY with CXS interface
  • UCIe Chiplet PHY & Controller
    • Compliant with the UCIe specification (2.0 & 1.1)
    • Flexible Structure, easy to customize (Pre-hardened PHY tuned to Customer Spec, PHY + Adapter Layer, PHY + Adapter Layer + Customized Protocol Layer)
    • Supports the CXS/AXI using the streaming package (AXI Interface bandwidth up to 89%)
    Block Diagram -- UCIe Chiplet PHY & Controller
  • UCIe Die-to-Die Controller IP
    • High Configurability and Customizability
    • Comprehensive Verification
    Block Diagram -- UCIe Die-to-Die Controller IP
  • D2D UCIe 1.1
    • Compatible with UCIe v1.1 specification
    • Features single-ended, source-synchronous, and DDR I/O signaling
    • Supports 32-bit (16-bits TX + 16-bit RX) data bus per module for standard packages
    • Offers a high clock frequency up to 16GHz
    Block Diagram -- D2D UCIe 1.1
  • D2D UCIe 1.0
    • Compatible with UCIe v1.0 specification
    • Single-ended, source synchronous and DDR IO Signaling
    • Supports 32 bits(16bits TX + 16bits RX) data bus per module for standard package
    • High clock frequency, up to 8GHz
    Block Diagram -- D2D UCIe 1.0
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