UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect

Overview

Key Features

• High data rate of 2–24 Gb/s
• Extremely low power of < 0.375 pJ/bit @ 2–16 Gb/s 0.5-V VDDQ
• Scalable IO voltage for optimizing channel performance
• Very low latency of < 2 ns PHY-to-PHY
• Support for many serialization and deserialization ratios including 4:1, 8:1, 12:1 and 16:1
• Support for bonded and independent slices
• Side band and redundancy support
• Staggered bump pitch for organic substrate (example macro above)
• Bump pitch customizable from 45um (advanced) to 180um (standard) package applications
• Each slice (TX+RX) macro area set by macro bump pitch (multiple slices can be stacked)
• Support for N/S and E/W Poly Orientations
• UCIe compatibility mode supports UCIe v1.1 FLIT Data Interface (FDI)
• Programmable alignment between link layer and PHY clocks to aid timing closure
• APB pclk pass-through to the link layer clock domain for reset of synchronous flops
• Integrated, background-calibrated DLL with duty-cycle correction for input clock
• Firmware-controlled startup and shutdown through control and status registers
• JTAG and/or APB register access
• Built in self-test (BIST) and diagnostic logic
• On Demand eye plotter
• Integrated microcontroller, PLL

Benefits

• Flexibly Configurable:
• BlueLynx™ PHY and link layer architecture is customizable to support a wide range of physical and complexed system bandwidth use cases.
• Supports many bump pitches, metal stacks, and poly orientations.
• Best in Class PPA:
• Achieve superior link power efficiency with ultralow voltage (300mV) support
• Operational Simplicity:
  • Flexible and robust APB bus and JTAG control interface
• Future Proof Design:
  • Our partners stay ahead of the competition with speed -of-software BlueLynx™ Generator technology next generation IP delivery. BlueLynx™ integrated microcontroller to support evolving chiplet interface standards.

Block Diagram

Applications

• Standard Organic and very advanced 2.5D package applications
• On-die Buses/Networks-on-Chip (NoCs) with various standards, including AXI4, AXI5 lite, CHI, ACE, and more.

Deliverables

• Hard macro with soft digital RTL
• IBIS model
• Integration Support
• Verilog Behavioral Model
• Timing Libraries
• Soft Digital RTL
• LEF
• CDL netlist
• DRC & LVS reports
• GDSII
• RTL Timing Constraints
• DFT Support for Scan

Technical Specifications