Chiplet Interconnect - Die-to-die interconnect IP solutions for advanced and standard packaging applications

Overview

Key Features

• High data rate of 2–24 Gb/s
• Very low power of < 0.375 pJ/bit @ 2–16 Gb/s 0.5-V VDDQ
• Very low latency of < 2 ns PHY-to-PHY
• Support for 2:1, 4:1, 8:1, 12:1 and 16:1 serialization and deserialization ratios
• Support for bonded and independent slices
• Side band and redundancy support
• Staggered bump pitch for organic substrate (example macro above)
• Bump pitch customizable from 45um (advanced) to 180um (standard) package applications
• Each slice (TX+RX) macro area set by macro bump pitch (multiple slices can be stacked)
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• Support for N/S and E/W Poly Orientations
• Programmable alignment between link layer and PHY clocks to aid timing closure
• APB pclk pass-through to the link layer clock domain for reset of synchronous flops
• Integrated, background-calibrated DLL with duty-cycle correction for input clock
• Firmware-controlled startup and shutdown through control and status registers
• JTAG and/or APB register access
• Built in self-test (BIST) and diagnostic logic
• On Demand eye plotter
• Integrated microcontroller, PLL

Benefits

• Customizable
  • BlueLynx PHY and link layer architecture is customizable to support a wide range of physical and complex system bandwidth use cases.
• Configurable
  • Whether your application is cost-sensitive or performance-intensive, BlueLynx offers versatile packaging options, including standard and advanced, with support for multiple bump pitches, metal stacks, and poly orientations.
• Optimized
  • BlueLynx D2D IP solutions offer power-optimized performance from 8 Gb/s to 16, 24, 32, and beyond.
• Multiple Processes
  • BlueLynx IP is available at 16nm,12nm, 7nm, 6nm, 5nm, 4nm, 3nm, and below across multiple semiconductor foundries and supports various medal stacks.
• Silicon Proven
  • Customers receive industry-standard ASIC integration views with reference collateral, including board package designs and a bring-up platform and software required for first-pass silicon success in the shortest time.

Technical Specifications