40G UltraLink D2D PHY

Overview

High-performance, low-latency PHY for D2D connectivity

The UltraLink™ Die-to-Die (D2D) PHY enables SoC providers to deliver more customized solutions that offer higher performance and yields while also shortening development cycles and reducing costs through greater IP reuse.

It is a mature solution that is silicon proven in multiple foundries and different process nodes.

Key Features

Innovative mixed-signal architecture to achieve high bandwidth, ultra low latency and low power
Flexible data rate from 20Gbps to 40Gbps
Built-in self-test features to ensure “known good die”
Interoperable between different technology nodes and foundries
Easy routing and straightforward integration
Achieves better than 10^-15 bit error rate (BER) without requiring forward error correction (FEC)
Integrated scrambling and lane de-skew functionality
Supports -40ºC to 125ºC industrial temperature range

Benefits

Ultra-Low Latency: Optimized for latency-sensitive applications
High Performance: 40Gbps wire speed delivers up to 1Tbps/mm unidirectional bandwidth
Cost Effective: Supports multi-chip module on organic substrates

Block Diagram

Technical Specifications

GLOBALFOUNDRIES

Silicon Proven: 12nm

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