Asynchronous SRAM IP
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UMC 0.45um Logic process standard gate array asynchronous high density single port SRAM memory compiler.
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UMC 0.5um Logic process standard asynchronous low density low power single port SRAM memory compiler.
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UMC 0.5um Logic process standard asynchronous low density low power two port (1R1W) SRAM memory compiler.
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UMC 0.45um Logic process standard gate array asynchronous embedded array high density two port (1R1W) SRAM memory compiler.