AHB compliant Cache controller IP
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10
IP
from 4 vendors
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10)
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32-Bit SPARC V8 Processor
- SPARC V8 instruction set with V8e extensions and compare-and-swap
- Advanced 7-stage dual-issue pipeline
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ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm
- Page Size – 2KB, 4KB, 8KB, 16KB
- Bank/chip select options
- Programmable timing
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ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
- Page Size – 2KB, 4KB, 8KB, 16KB
- Bank/chip select options
- Programmable timing
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ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 12nm
- Page Size – 2KB, 4KB, 8KB, 16KB
- Bank/chip select options
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32-bit CPU IP core supporting ISO 26262 ASIL B level functional safety for automotive applications
- 32-bit CPU IP core that supports ISO 26262 ASIL B level functional safety for automotive applications
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64-bit High performance Dual Core Microprocessor
- RISC-V 64G (RV64IMAFD) ISA
- 13-16 stage out-of-order pipeline implementation
- Advanced branch predictor: BTB, BHT, RAS
- Harvard architecture
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64-bit High performance Single Core Microprocessor
- RISC-V 64G (RV64IMAFD) ISA
- 13-16 stage out-of-order pipeline implementation
- Advanced branch predictor: BTB, BHT, RAS
- Harvard architecture
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MIPI LLI Controller - (Low Latency Interface)
- Compliant with MIPI LLI Rev 1.0 and M-PHY Type 1 Rev 2.0
- Interfaces to on-chip interconnect infrastructure, like AHB or AXI or OCP buses
- Configurable to provide any or all of the following interfaces for the named traffic classes
- Provides AHB/AXI/OCP Slave Interface for PHY Adapter Layer management
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64-bit High performance Quad Core RISC-V Microprocessor
- RISC-V 64G (RV64IMAFD) ISA
- 13-16 stage out-of-order pipeline implementation
- Advanced branch predictor: BTB, BHT, RAS
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64-bit RISC-V Single Core Microprocessor
- RISC-V 64G (RV64IMAFD) ISA
- 6 stage in-order pipeline implementation
- Advanced branch predictor: BTB, BHT, RAS
- Harvard architecture
