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AHB compliant Cache controller IP

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Search (17)
Compare 17 IP from 6 vendors (1 - 10)
  • CXL CONTROLLER IIP
    • Compliant with CXL 1.0/1.1 Specifications
    • Supports Native PCIe mode and below features as defined in the PCIe specification
    • PCIE Express specs 1.0/2.0/3.0/4.0/5.0
    • PIPE interface
    Block Diagram -- CXL CONTROLLER IIP
  • ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
    • Page Size – 2KB, 4KB, 8KB, 16KB
    • Bank/chip select options
    • Programmable timing
    Block Diagram -- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
  • ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm
    • Page Size – 2KB, 4KB, 8KB, 16KB
    • Bank/chip select options
    • Programmable timing
    Block Diagram -- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm
  • ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 12nm
    • Page Size – 2KB, 4KB, 8KB, 16KB
    • Bank/chip select options
    Block Diagram -- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 12nm
  • ONFI 4.0 NAND Flash Controller & PHY
    • • Support ONFI 4.0, EZ – NAND, Standard ClearNAND, Advanced ClearNAND
    • • Support standard asynchronous NAND flash
    • • High performance from 40MT/s to 800MT/s
    • • High density NAND flash up to 1024 Gb
    Block Diagram -- ONFI 4.0 NAND Flash Controller & PHY
  • MIPI LLI Controller - (Low Latency Interface)
    • Compliant with MIPI LLI Rev 1.0 and M-PHY Type 1 Rev 2.0
    • Interfaces to on-chip interconnect infrastructure, like AHB or AXI or OCP buses
    • Configurable to provide any or all of the following interfaces for the named traffic classes
    • Provides AHB/AXI/OCP Slave Interface for PHY Adapter Layer management
    Block Diagram -- MIPI LLI Controller - (Low Latency Interface)
  • 32-Bit SPARC V8 Processor
    • SPARC V8 instruction set with V8e extensions and compare-and-swap
    • Advanced 7-stage dual-issue pipeline
  • USB2.x HOST IIP
    • Compliant with USB 2.0 specification.
    • Compliant with USB 2.0 Enhanced Host Controller Interface (EHCI) Rev 1.0
    • Asynchronous Park-mode
    • Three caching models: no caching, micro-frame caching and frame caching
    Block Diagram -- USB2.x HOST IIP
  • USB2.x OTG IIP
    • Compliant with USB 2.0 specification.
    • Compliant with USB 2.0 Enhanced Host Controller Interface (EHCI) Rev 1.0
    • Asynchronous Park-mode
    • Three caching models: no caching, micro-frame caching and frame caching
    Block Diagram -- USB2.x OTG IIP
  • USB2.x DEVICE IIP
    • Compliant with USB 2.0 specification.
    • Compliant with USB 2.0 Enhanced Host Controller Interface (EHCI) Rev 1.0
    • Asynchronous Park-mode
    • Three caching models: no caching, micro-frame caching and frame caching
    Block Diagram -- USB2.x DEVICE IIP
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