AndesCore™ D25F-SE is a 32-bit CPU IP core that supports ISO 26262 ASIL B level functional safety for automotive applications. Approved based on the functional safety assignments of a Safety Element Out-of-Context (SEooC), which includes the ISO 26262 compliant development process and the qualitative approach with respect to hardware safety analysis, D25F-SE is certified to be used in safety-related applications.
Based on AndeStar™ V5 architecture that incorporated RISC-V technology, D25F-SE is capable of delivering high per-MHz performance and operating at high frequencies with small gate count. It supports the RISC-V P-extension (draft) DSP/SIMD ISA contributed by Andes, single-/ double-precision floating point and bit-manipulation instructions, branch prediction for efficient branch execution, Instruction and Data caches, local memories for low-latency accesses, and ECC for memory error protection. Features also includes RISC-V Platform Level Interrupt Controller, AXI 64-bit or AHB 64/32-bit system bus, WFI mode for low power and power management, and JTAG debug interface.
Functional Safety
- For DPS processing and general-purpose control of embedded systems in automotive applications
- Compliant with ISO 26262:2018 standard parts 2, 4, 5, 8 and 9 for ASIL (Automotive Safety Integrity Level) B
- Independent assessment and certification by SGS-TÜV Saar GmbH
- AndesCore™ D25F-SE ISO 26262 compliant certificate
Key Features and Performance
ISO 26262 Functional Safety
| Key Features | Benefits |
|---|---|
| Certified according to ISO 26262:2018 edition series of standards | Compliant with the latest version of standards |
| Andes Technology Development Process certified by parts 2, 4, 5, 6, 8 and 9 of the standards for components up to ASIL D | To prevent systematic failures |
| AndesCore™ D25F-SE CPU IP certified by parts 2, 4, 5, 8 and 9 of the standards in compliance with ASIL B requirements | To prevent random hardware failures |
| Supporting internal and external safety mechanisms; including qualitative DFMEA (Design Failure Mode and Effects Analysis) and quantitative FMEDA (Failure Modes, Effects, and Diagnostic Analysis) evaluations | Facilitate functional safety product integration and certification |
| Certified by SGS-TÜV Saar GmbH, with DAkkS logo | Audited independently by credible third-party certification body |
AndeStar™ V5 Architecture
| Key Features | Benefits |
|---|---|
| RISC-V RV32GCBP Instructions |
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| RISC-V P-extension (draft) DSP/SIMD instructions with versatile operations | Boost the performance of voice, audio, image and signal processing |
| RISC-V single and double precision floating point instruction | Accelerate the processing of high precision arithmetic |
| RISC-V bit-manipulation instructions, including the Zba, Zbb, Zbc and Zbs extensions | Benefits codes with bit-wise operations |
| Andes Extended Instructions | Andes exclusive performance and functionality enhancements |
| 16/32-bit mixable instruction format | For compact code density |
| 32 general-purpose registers | For better code size and performance |
| Machine (M) and User (U) Privilege levels | Embedded systems with privilege protections |
CPU Core
| Key Features | Benefits |
|---|---|
| 3.57 Coremark/MHz, 1.91 DMIPS/MHz* | Superior performance-per-MHz |
| 5-stage pipeline, with a full-cycle reserved for critical SRAM accesses | Superior performance-efficiency, while allowing for high speeds |
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Extensive branch prediction features
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| Physical Memory Protection (PMP), 16 regions | Basic read/write/execute memory protection with minimum cost |
| Performance monitors | Program code performance tuning |
| StackSafe™ hardware stack protection |
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Multiplier options
|
Option to choose between speed and area according to application's requirements |
| QuickNap™ technology | Fast power-down/wake-up support for caches |
* AndeSight v500, DMIPS/MHZ follow Dhrystone’s no-inline ground rules, best performances
Memory Subsystems
| Key Features | Benefits |
|---|---|
|
I-Cache & D-Cache
|
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ILM & DLM
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| Soft-error protection: ECC for I-Cache and D-Cache, ILM and DLM with SRAM interface | Code and data integrity protection |
| Bus manager port: AXI with 64-bit data or AHB with 64 or 32-bit data | User-selectable bus interface for optimal efficiency |
| Bus subordinate port: AHB with 64 or 32-bit data, for ILM/DLM accesses, with Low Latency mode option | Efficient data transfer between CPU and SoC managers |
| Core/bus clock ratio of N:1 | Simplified SoC integration |
Platform-Level Interrupt Controller (PLIC)
| Key Features | Benefits |
|---|---|
|
Implements RISC-V PLIC specification
|
Allow individual interrupts to be serviced and prioritized without sharing |
Debug Support
| Key Features | Benefits |
|---|---|
| Implements RISC-V debug specifications | Supported by industry debug tool suppliers |
| JTAG Debug Port | Industry-standard support |
| Embedded Debug Module with up to 8 triggers | Flexible configurations to tradeoff between gate count and debugging capabilities |
| Exception redirection support | Entering debugger upon selected exceptions without using breakpoints |
