32-bit Multiprocessor with Level-2 Cache-Coherence

Overview

AndesCore™ A25MP 32-bit multicore CPU IP is based on AndeStar™ V5 architecture. It supports RISC-V standard ‘IMAC-FD’ extensions, Andes contributed DSP/SIMD 'P' extension (draft), user-level interrupt 'N' extension, and Andes performance/functionality enhancements such as instructions for faster memory accesses, faster branch handling, and Andes Custom Extension™ (ACE) to add user defined instructions. It features MMU for Linux based applications, branch prediction for efficient branch execution, level-1 instruction/data caches and local memories for low-latency accesses.

The A25MP symmetric multiprocessor supports up to 4 cores and a level-2 cache controller with instruction and data prefetch. Andes Coherence Unit (ACU) manages level-1 cache coherence including I/O coherence for cacheless bus masters, and duplicated L1 tag to screen allocated lines for snoop queries. Other A25MP features include ECC for level-1/2 memory soft error protection, Platform-Level Interrupt Controller (PLIC) with enhancements for vectored dispatch and priority-based preemption, CoDense™, StackSafe™ for software quality improvement, and QuickNap™, PowerBrake, and WFI for power management.

Key Features

Symmetric multiprocessing up to 4 cores
Level-2 cache and cache coherence support
AndeStar™ V5 Instruction Set Architecture (ISA). Compliant to RISC-V ISA IMACFDN, with Andes performance/functionality extensions
Floating point extensions
DSP/SIMD ISA to boost the performance of voice, audio, image and signal processing
Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
32-bit, 5-stage pipeline CPU architecture
16/32-bit mixable instruction format for compacting code density
Branch predication to speed up control code
Return Address Stack (RAS) to speed up procedure returns
Memory Management Unit (MMU) and Physical Memory Protection (PMP)
Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
Enhancement of vectored interrupt handling for real-time performance
Advanced CoDense™ technology to reduce program code size

Benefits

Performance
- Symmetric multiprocessing up to 4 cores
- Level-2 cache and cache coherence support
- AndeStar™ V5 Instruction Set Architecture (ISA). Compliant to RISC-V ISA IMACFDN, with Andes performance/functionality extensions
- Floating point extensions
- DSP/SIMD ISA to boost the performance of voice, audio, image and signal processing
- Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
- 32-bit, 5-stage pipeline CPU architecture
- 16/32-bit mixable instruction format for compacting code density
- Branch predication to speed up control code
- Return Address Stack (RAS) to speed up procedure returns
- Memory Management Unit (MMU) and Physical Memory Protection (PMP)
- Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
- Enhancement of vectored interrupt handling for real-time performance
- Advanced CoDense™ technology to reduce program code size
Flexibility
- Multiprocessing up to 4 CPU cores with hardware managed memory coherence including non-cache bus master
- Easy arrangement of preemptive interrupts
- StackSafe™ hardware to help measuring stack size, and detecting runtime overflow/underflow
- Versatile configurations to tradeoff between core size and performance requirements
Power Management
- PowerBrake, QuickNap™ and WFI (Wait For Interrupt) for different power saving occasions

Block Diagram

Applications

High performance solid state drives
Advanced Driver-Assistance Systems
Network communications

Deliverables

A25MP with 1, 2 or 4 Processor(s) and AE350 Platform
- Pre-integrated A25MP CPU subsystem, PLIC, Debug Module, and AXI Platform

Technical Specifications

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