25g 50g ethernet IP

The 50G Ethernet Intel® FPGA IP core implements the 25G & 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium and the IEEE 802.3by 25Gb Ethernet draft
The IP core includes an option to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard
The MAC client side interface for the 50 Gbps Ethernet IP core is a 128-bit Avalon® streaming interface (Avalon-ST)

This IP core implements the 25G and 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium
The IP core includes an option to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard. The media access control (MAC) client side interface for the 25GbE IP core is a 64 bit Avalon® streaming interface (Avalon-ST)
It maps to one 25.78125 Gbps transceiver
The IP core optionally includes Reed-Solomon forward error correction (FEC) for support of direct attach copper (DAC) cable.

OmegaCORE 800G DX is a multi-channel, multi-rate Ethernet aggregator that supports tributaries from 10GE to 800GE, utilizing 112G/s SerDes and 56G/s SerDes.
The supported Ethernet protocols are 10G, 25G, 40G, 50G, 100G, 200G, 400G, 800G and 10GFC, 16GFC, 32GFC, 64GFC, 128GFC, 256GFC, as well as FEC framing of FlexO-1/2/4-SR.

The 10G-100G_ZX is a multi- channel, multi-rate Ethernet aggregator that supports tributaries in combinations up to 100G utilizing the 112G/s SerDes, 56G/s SerDes and 25G/s SerDes.

25G 50G Ethernet IP