IP Catalog > Interface IP > Interconnect IP > Ethernet IP > Ethernet MAC IP > Simulation VIP for Ethernet up to 800G

Simulation VIP for Ethernet up to 800G

Overview

Mature and highly capable compliance verification solution.

Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for the Ethernet 800G protocol provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in test benches at IP, system-on-chip (SoC), and system levels, the VIP for Ethernet 800G helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP for Ethernet 800G runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM).

The VIP for Ethernet 800G enables verification of Ethernet interfaces in MAC standalone and full-stack mode for speeds up to 800Gbps at different levels:

Supported specifications: Ethernet Technology Consortium r1.0, IEEE 802.3-2018, IEEE 802.3cd-2018 50G, IEEE 802.3ck 100G, IEEE 802.3by 25G, USXGMII Cisco spec version 2.12 for multi-port and 2.2 for a single port, USGMII Cisco spec version 3.0

Key Features

  • 800Gbps Interfaces
    • 800Gbps Ethernet interfaces based on Ethernet Technology Consortium supports:
      • 800GMII
      • 800GBase-R Dual-PCS 32 lanes (25Gb/s)
      • RS FEC(544,514)
      • PMA(4:1 Mux) - 8x106.25G, 16x53.125G
      • PMD interfaces - 2x400GBASE-DR4 modules
      • Multi-lane distribution (MLD) to distribute data from a single Media Access Control (MAC) channel across 2x16 PCS lanes
      • Compliance mode
      • Customized Alignment Markers
      • Full duplex operation
      • Internal and external clock mode
      • PAM4 modulation scheme
    • 100GPL Features
      • 100GPL interface supported on IEEE802.3ck supports:
        • 100GKR1/100GCR1
        • 200GKR2/200GCR2
        • 400GKR4/400GCR4
        • Interleaved RS FEC supported for 100GKR1/100GCR1
        • Auto-negotiation supported for all PHY types
        • PMD link training supported
        • Single clock mode supported
        • Block lock FSM implemented
      • 400Gbps Interfaces
        • 400Gbps Ethernet interfaces based on IEEE 802.3bs
          • 400GMII
          • 400GBase-R PCS and PMA
          • PMD interfaces
            • 400GBase-SR16
            • 400GBase-FR8/400GBase-LR8
            • 400GBase-DR4
          • RS FEC
          • Energy-Efficient Ethernet
        • 200Gbps Interfaces
          • 200Gbps Ethernet interfaces based on IEEE 802.3bs
            • 200GMII
            • 200GBase-R PCS and PMA
            • PMD interfaces: 200GBase-DR4/200GBase-FR4/200GBase-LR4/200GBase-KR4/200GBase-CR4/200GBase-SR4
            • RS FEC
            • PMD training
            • Energy-Efficient Ethernet
            • LL FEC for 200GBASE-CR4 / KR4
          • 100Gbps Interfaces
            • 100Gbps Ethernet interfaces based on IEEE 802.3-2018
              • CGMII
              • 00GBase-R PCS and PMA
              • PMD interfaces
                • 100GBase-CR10/100GBase–SR10
                • 100GBase-CR4/100GBase-KR4/100GBase-KP4
                • 100GBase-KR2/100GBase-CR2/100GBase-SR2
                • 100GBase-DR
              • RS FEC
              • Fire-code FEC
              • Supports PMD training
              • Backplane auto-negotiation
              • Energy-Efficient Ethernet
              • LL FEC for 100GBASE-CR4 / KR4
            • 50Gbps Interfaces
              • 50Gbps Ethernet interfaces based on IEEE 802.3-2018 and 25/50 Gigabit Ethernet Consortium
                • 50GMII
                • 50Gbase-R PCS and PMA
                • Fire-code FEC
                • RS FEC
                • PMD interfaces: 50GBase-KR/50GBase-CR/50GBase-S
                • Back-plane auto-negotiation
                • PAM4/NRZ lane encoding/decoding
                • Energy-Efficient Ethernet
                • LL FEC for 50GBASE-R
              • 40Gbps Interfaces
                • 40Gbps Ethernet interfaces based on IEEE 802.3-2018
                  • XLGMII
                  • 40Gbase-R PCS and PMA
                  • Fire-code FEC
                  • PMD interfaces: 40GBase-KR4/40GBase-CR4/40GBase-SR4
                  • Backplane auto-negotition
                  • Energy-Efficient Ethernet
                • 25Gbps Interfaces
                  • 25Gbps Ethernet interfaces based on IEEE 802.3by-2016 and 25 Gigabit Ethernet Consortium
                    • 25GMII
                    • 25GBase-R PCS and PMA
                    • Fire-code FEC
                    • RS FEC
                    • PMD interfaces: 25GBase-CR/25GBase-KR
                    • Back-plane auto-negotiation
                    • Energy-Efficient Ethernet
                    • Block lock FSM implemented
                    • Customized SDR mode on XGMII interface.
                  • 10Gbps Interfaces
                    • 10Gbps Ethernet interfaces based on IEEE 802.3-2018
                      • XGMII
                      • 10GBase-R and XSBI PCS and PMA
                      • 10GBase-KR/10GBase-KX4
                      • XAUI
                      • RXAUI with 10/20/40bit per lane
                      • Fire-code FEC for 10GBase-KR
                      • PMD training
                      • Backplane auto-negotiation for 10GBase-KX4 and 10GBase-KR
                      • Energy-Efficient Ethernet
                      • USXGMII interfaces: Single-Port and Multi-Port (with RS-FEC)
                      • PCH feature for USXGMII
                      • Block lock FSM implemented
                      • Customized SDR mode on XGMII interface.
                    • 1Gbps Interfaces
                      • 1Gbps Ethernet interfaces based on IEEE 802.3-018
                        • GMII
                        • 1000Base-KX
                        • TBI
                        • QSGMII Rev 1.2
                        • SGMII Rev 1.8
                        • USGMII: QSGMII, OSGMII
                        • RGMII
                        • Clause 73 backplane auto-negotiation
                        • Clause 37 auto-negotiation
                        • Full-duplex and half-duplex operation
                        • Energy-Efficient Ethernet
                      • 10/100Mbps Interfaces
                        • 10/100Mbps Ethernet interfaces based on IEEE 802.3-2018: MII and RMII
                      • Dynamic Switching
                        • Supports run-time speed switching
                      • PMA Bus-Width
                        • Configurable PMA bus width: 2, 4, 8, 10, 16, 20, 32, 40, 64, 66, 80 (SCM), and 128 (SCM, 10G and above speed) bits
                      • Clock, Jitter, Drift
                        • Single Clock mode only for selected interfaces and speeds
                        • Support for external clock mode
                        • Supports CDR for serial interfaces
                        • Support for internal clock mode for parallel bus-width interfaces
                        • Jitter and skew support in internal clock mode
                        • Auto-detection and correction of clock frequency drift in internal clock mode
                      • Flow Control
                        • Supports pause FC and PFC pause FC
                      • Frames
                        • Supports the following frame types:
                          • Ethernet 802.3 (Type and Length defined)
                          • Jumbo frame
                          • MAGIC frame
                          • Version II frame
                          • Pause frame
                          • PFC Pause frame
                          • Management frame
                          • Tagged Frame:
                            • Single Tagged (Q-VLAN tag and S-VLAN tag)
                            • Double tagged (S-VLAN tag and Q-VLAN tag)
                          • Upper Layer Frames: TCP, UDP, IPV4, IPV6, SNAP, MPLS, FC, MACSEC
                        • Custom Frame
                          • Proprietary header support
                        • MDIO Interface
                          • Supports MDIO interface as per Clause 22 and Clause 45
                        • PHY Timestamping
                          • Supported for 10GBaser and 25Baser interfaces

                          Block Diagram

                          Simulation VIP for Ethernet up to 800G Block Diagram

                          Technical Specifications

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