32-Bit Microprocessor IP
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Open-source compact microcontroller core with a 4-stage in-order pipeline for deeply embedded applications
- SCR1 is an open-source and silicon-proven RISC-V-compatible, 32-bit, entry-level, MCU-class core. It targets general-purpose, deeply embedded applications and control systems.
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Efficient microcontroller core with a 5-stage in-order pipeline, privilege modes, an MPU, L1 and L2 caches
- SCR3 is an efficient, silicon-proven, microcontroller-class, 32/64-bit RISC-V processor core.
- It is optimized for power-sensitive, small-area, embedded applications, that demand high performance.
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Efficient microcontroller core with a 5-stage in-order pipeline, privilege modes, an FPU, an MPU, L1 and L2 caches
- SCR4 is a 32/64-bit RISC-V low-power, high-performance, area-optimized processor core with floating-point arithmetic functionality.
- The SCR4 core fully supports RISC-V standard "I" Integer, "M" Integer Multiplication and Division, "A" Atomic, "C" 16-bit Compressed, "F" Single-Precision Floating-Point, "D" Double-Precision Floating-Point, “B” Bit Manipulation, and “K” Scalar Cryptography extensions.
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High-performance microcontroller core with a 12-stage dual-issue out-of-order pipeline and a high performance FPU
- SCR6 is a high-performance, silicon-proven, 64-bit RISC-V processor core. It is optimized for embedded RTOS-based applications, that require considerable computational power.
- The SCR6 core supports RISC-V standard "I" Integer, "M" Integer Multiplication and Division, "A" Atomic, "C" 16-bit compressed, "F" Single-Precision Floating-Point, "D" Double-Precision Floating-Point, "B" Bit Manipulation, and "K" Scalar Cryptography extensions.
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Efficient Linux-capable application core with a 9-stage in-order pipeline, an MMU, L1 and L2 caches, and cache coherency
- SCR5 is an efficient, silicon-proven, entry-level Linux-capable 32/64-bit RISC-V processor core.
- The SCR5 core fully supports RISC-V standard "I" Integer, "M" Integer Multiplication and Division, "A" Atomic, "C" 16-bit Compressed, "F" Single-Precision Floating-Point, "D" Double-Precision Floating-Point, “B” Bit Manipulation, and “K” Scalar Cryptography extensions.
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Compact High-Speed 32-bit CPU Core
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- Floating point extensions
- Andes extensions, architected for performance and functionality enhancements
- Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
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32-bit SPARC V8 processor
- The LEON3 processor offers robust fault tolerance and performance for space and high-reliability applications, including satellites and scientific instruments.
- The LEON3 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable and particularly suitable for system-on-a-chip (SOC) designs.
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Tensilica ConnX 110/120
- Certified ISO 26262:2018 ASIL-compliant
- VLIW parallelism issuing multiple concurrent operations per cycle
- 128-bit or 256-bit SIMD
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Tensilica ConnX B10/B20
- Single-instruction, multiple-data (SIMD) vector processing
- Up to 5-issue very long instruction word (VLIW) for parallel load/store, MAC, and ALU ops
