32-Bit Microprocessor IP

Compare 115 32-Bit Microprocessor IP from 22 vendors (1 - 10)

Tensilica ConnX 110/120
- Certified ISO 26262:2018 ASIL-compliant
- VLIW parallelism issuing multiple concurrent operations per cycle
- 128-bit or 256-bit SIMD
Tensilica ConnX B10/B20
- Single-instruction, multiple-data (SIMD) vector processing
- Up to 5-issue very long instruction word (VLIW) for parallel load/store, MAC, and ALU ops
Tensilica Fusion F1 DSP
- Specialized design to take advantage of sparsity in weights and activations for compute and bandwidth reduction
Data Movement Engine - Efficient data-processing and simultaneous multi-threading, low latency and deterministic data access
- Efficient throughput with the first RISC-V core to support up to 4-way multithreading
- Highly scalable multi-core, multi-cluster coherent computing solution
- MIPS Enhancements for increased connectivity and throughput
- Use in 5G/6G Comms Infrastructure, Automotive Gateways, Embedded & Datacenter
512-bit Vector DSP IP, Single Core with Functional Safety
- Integrated hardware safety features with minimal area and power impact for full ASIL compliance (ASIL D systematic, up to ASIL C random)
- Four-way VLIW architecture combining scalar and vector operations
- 128-bit, 256-bit and 512-bit vector lengths
- 8, 16, and 32-bit integer SIMD engines
512-bit Vector DSP IP, Quad Core with Functional Safety
- Integrated hardware safety features with minimal area and power impact for full ASIL compliance (ASIL D systematic, up to ASIL C random)
- Four-way VLIW architecture combining scalar and vector operations
- 128-bit, 256-bit and 512-bit vector lengths
- 8, 16, and 32-bit integer SIMD engines
512-bit Vector DSP IP, Dual Core with Functional Safety
- Integrated hardware safety features with minimal area and power impact for full ASIL compliance (ASIL D systematic, up to ASIL C random)
- Four-way VLIW architecture combining scalar and vector operations
- 128-bit, 256-bit and 512-bit vector lengths
- 8, 16, and 32-bit integer SIMD engines
256-bit Vector DSP IP, Single Core with Functional Safety
- Integrated hardware safety features with minimal area and power impact for full ASIL compliance (ASIL D systematic, up to ASIL C random)
- Four-way VLIW architecture combining scalar and vector operations
- 128-bit, 256-bit and 512-bit vector lengths
- 8, 16, and 32-bit integer SIMD engines
128-bit Vector DSP IP, Single Core with Functional Safety
- Integrated hardware safety features with minimal area and power impact for full ASIL compliance (ASIL D systematic, up to ASIL C random)
- Four-way VLIW architecture combining scalar and vector operations
- 128-bit, 256-bit and 512-bit vector lengths
- 8, 16, and 32-bit integer SIMD engines
512-bit Vector DSP IP, Single Core
- Four-way VLIW combining scalar and vector operations
- 128-bit, 256-bit and 512-bit vector word lengths
- 8, 16, and 32-bit integer SIMD engines
- IEEE 754-compliant vector floating point unit option offers single-precision or half-precision operations and advanced math functions