32-Bit Microprocessor IP
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32-Bit Automotive Processor - 3-Stage Pipeline, Single/Dual-issue
- NA300 series processor is a ISO26262 ASIL-B/D Certified RISC-V CPU IP,Nuclei self-developed STL supports multiple ASIL-B automotive use cases.
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AI DSA Processor - 9-Stage Pipeline, Dual-issue
- NI900 is a DSA processor based on 900 Series.
- NI900 is optimized with features specifically targeting AI applications.
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32-Bit Automotive Processor - 9-Stage Pipeline, Dual-issue
- NA900 series processor is the 1st ISO26262 ASIL-B/D Product Certified RISC-V CPU IP, Nuclei self-developed STL supports multiple ASIL-B automotive use cases.
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32-Bit Security processor
- Nuclei Security processor is a series of chips designed specifically for security application scenarios, including NS100, NS300, and NS600 products.
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32-Bit Low Power Processor - 2-Stage Pipeline, Single-issue
- N200 Series is designed for deeply embedded application with low power and area consumption.
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32-Bit High Performance Processor - 2-Stage Pipeline, Single-issue
- With extreme low area, N100 is a 32b RISC-V processor designed specifically for low power application.
- N100 aims for cost sensitive application including IoT, MCU, sensor.
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32-Bit High Efficiency Processor - 3-Stage Pipeline, Single/Dual-issue
- N300 Series is a 32-bit RISC-V processor designed for applications requiring extreme energy efficiency and DSP/FPU features.
- N300 Series can be applied to AIoT, embedded and industrial control, etc.
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Open-source compact microcontroller core with a 4-stage in-order pipeline for deeply embedded applications
- SCR1 is an open-source and silicon-proven RISC-V-compatible, 32-bit, entry-level, MCU-class core. It targets general-purpose, deeply embedded applications and control systems.
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Efficient microcontroller core with a 5-stage in-order pipeline, privilege modes, an MPU, L1 and L2 caches
- SCR3 is an efficient, silicon-proven, microcontroller-class, 32/64-bit RISC-V processor core.
- It is optimized for power-sensitive, small-area, embedded applications, that demand high performance.
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Efficient microcontroller core with a 5-stage in-order pipeline, privilege modes, an FPU, an MPU, L1 and L2 caches
- SCR4 is a 32/64-bit RISC-V low-power, high-performance, area-optimized processor core with floating-point arithmetic functionality.
- The SCR4 core fully supports RISC-V standard "I" Integer, "M" Integer Multiplication and Division, "A" Atomic, "C" 16-bit Compressed, "F" Single-Precision Floating-Point, "D" Double-Precision Floating-Point, “B” Bit Manipulation, and “K” Scalar Cryptography extensions.
