The SafeSPI is a secure version of the SPI protocol that has been designed to provide enhanced security features, making it suitable for use in sensitive applications. Error detection through the SPI is crucial in ensuring the safety and reliability of airplanes. The SafeSPI protocol ensures that all data transfer is performed securely, preventing any unauthorized access to the transmitted data.
- SafeSPI supports CRC (Cyclic Redundancy Check).
- SafeSPI provides the capability to transfer the data in packet format.
- SafeSPI supports backdoor access for memory and registers.
- SafeSPI supports bit encodings.
Cyclic Redundancy Check, is a common method used in SPI communication to verify the integrity of data transmitted between the master and slave devices. It is a type of checksum calculated by the transmitter over a specific portion of the data.
SafeSPI, the master and peripheral devices exchange a set of cryptographic keys during the initialization phase, which is used to encrypt and authenticate the data transmitted between them. This ensures that only authorized devices can participate in the communication and that the data exchanged is not modified or tampered with during the transmission.
Product Specifications :
- Fully synthesizable Register Transfer Level (RTL) Verilog HDL core.
- Test Bench. (Environment Variable : UVM)
- Targeted FPGA Xilinx Series 7 FPGA
- Clock Frequency : IP core clocks are adjustable (60 MHz for internal)
- Standard IO
Product Options :
- Adaptations : Dual - SafeSPI two data lines are available for data transfer
- 8 / 64 Bit Standard Microcontroller Interface possible.
- Add - ons : Verification IP - UVM VIP.
