Slave serial interface compatible with the popular SPI standard. Permits an SPI Master to communicate with your FPGA, CPLD or ASIC device.
The controller uses a series of registers as a data structure to communicate between Master and Slave.
SPI Slave Serial Interface Controller
Overview
Key Features
- SPI compliant
- Simple SPI programming
- Configurable number of config registers
- Configurable number of status registers
- Configurable clock polarity (CPOL)
- Configurable clock phase (CPHA)
Benefits
- Technology independent soft IP Core
- Suitable for FPGA, SoC and ASIC
- Supplied as human-readable source code
- One-time license fee with unlimited use
- Field tested and market proven
- Any custom modification on request
Block Diagram
Deliverables
- VHDL source-code (or Verilog on request)
- Simulation test bench
- Examples and scripts
- Full pdf datasheet
- One-to-one technical support
- One years warranty and maintenance
Technical Specifications
Foundry, Node
All
Availability
Immediate
Related IPs
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- SPI XIP Flash Memory Controller IP – Programmable IO & Execute-In-Place (XIP) via second AMBA Interface
- A bridge to convert the slave SPI interface to the master I2C interface and vice versa
- A bridge to convert the slave SPI interface to the master UART interface and vice versa