Spacewire Codec with AHB host interface

Overview

The GRSPW core implements a Spacewire Codec with RMAP support and AMBA host interface. The core implements the Spacewire standard with the protocol identification extension (ECSS-E- 50-12 part 2) and RMAP protocol draft C. Receive and transmit data is autonomously transferred between the Spacewire Codec and the AMBA AHB bus using DMA transfers. Through the use of receive and transmit descriptors, multiple Spacewire packets can be received and transmitted without CPU involvement. The GRSPW control registers are accessed through an APB interface. For critical space applications, a fault-tolerant (FT) version of GRSPW is available with full SEU protection of all RAM blocks.

Key Features

Full implementation of Spacewire standard
Protocol ID extension ECSS-E-50-12 part 2
Optional RMAP protocol draft C
AMBA AHB back-end with DMA
Descriptor-based autonomous multi-packet transfer
Low area and high frequency
SEU protection fault-tolerance
Portable
2,800 Cells on RTAX2000S FPGA, 10,000 ASIC gates
100 MBit/s on RTAX, 400 MBit/s on ASIC
VHDL source code or netlist delivery

Benefits

Tested and verified against several other SPW cores
Low area and high frequency
Easily portable between FPGA and ASIC
Low-cost project license
SEU protection of all RAM blocks

Block Diagram

Deliverables

VHDL source code or FPGA/ASIC netlist
Stand-alone testbench
Optional plug&play interface for GRLIB IP Library
User's Manual

Technical Specifications

Foundry, Node

Any

Maturity

Fully validated on silicon

Availability

Now

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