Standard SPI Single Master

Overview

The SPIMmodule is part of Inicore's IPmodule family. The serial peripheral interface (SPI) protocol is often used to connect peripheral devices to a CPU. Several slave devices can be connected to the same bus. Since it is a serial bus, the pin count is low.
The SPIMmodule is a single master controller and uses a message queue based architecture. A message consists of the command, transmit data and receive data field. The command field defines the length of the SPI access (1-32 bits, or
continued in the next command), the selected slave device, the SS to SCK delay and the delay after transfer control. Using the queue, several SPI commands can be executed without CPU interaction.
A range of messages can be selected to be sent by the SPI controller. There is a wrap mode to enable continuously sending the same messages.
The SPI controller supports all standard modes. The clock phase and clock polarity can be configured as well as the bit rate and slave select polarity.

Key Features

Standard SPI single master
Full duplex operation
Programmable frame length (4-16-bit, 24-bit, 32-bit, cont.)
Programmable transfer delay
Programmable peripheral select to serial clock delay
Programmable peripheral slave selects
Continous re-transfer mode
Supports all SPI modes (0,0 / 1,0 / 0,1 / 1,1)

configurable clock phase
configurable clock polarity and phase

Message queue buffer

supports autonomous message transmission
selsctable message buffer size
message buffer is 32-bit wide

Independent programmable bitrate generator
Local interrupt controller
Supports synchronous bus interfaces such as AMBA APB version 2.0
Full synchronous design
Synthesis Options:

CPU readback enable
Number of slave selects
Message queue depth

Benefits

For gate-count optimization, the core can be configured to disable the configuration register read-back path. The depth of the message queue as well as the number of slave devices can be selected prior to synthesis. The core supports replacing the register files used for the message buffer with on-chip memories.
Using a separate APB wrapper, the core can be easily integrated into ARM based systems.

Block Diagram

Applications

Industrial control
System-on-Chip
Peripheral Logic
Embedded Systems

Deliverables

VHDL or Verilog RTL Source Code
Functional Testbench
Synthesys Script
Data Sheet
User Guide
Hotline Support by means of phone, fax and e-mail

Technical Specifications

Foundry, Node

Technology independent

Maturity

Proven in ASIC and FPGA Technologies

Availability

now

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